MemPalace Task Handoff
MemPalace/mempalace
Creates, hands off, claims, executes and closes agent tasks through the MemPalace logstream, with approval of the exact task before it is recorded.
A skill your agent uses when the user needs Vivado implementation strategy selection or optimization.
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a claude-codeProject install by default; add -g for ~/.claude/skills/.
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-impl --agent claude-codeProject scope by default; add --scope user for a personal install. Needs GitHub CLI 2.90.0 or later (public preview).
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .claude/skills && cp -r skills-src/vivado-impl .claude/skills/vivado-impl && rm -rf skills-srcUse ~/.claude/skills/ instead of .claude/skills for a personal install. The folder must contain SKILL.md.
Claude Code skills documentation · loads skills from .claude/skills/
Install the "vivado-impl" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-impl into .claude/skills/vivado-impl/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-impl", then confirm the skill loads.Claude Code copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.
$skill-installer install https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-implType this inside Codex. $skill-installer <name> installs a curated skill from openai/skills. The installer writes to $CODEX_HOME/skills (default ~/.codex/skills). Restart Codex if the skill does not show up.
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a codexProject install goes to .agents/skills/; add -g for ~/.codex/skills/.
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-impl --agent codexProject scope by default (.agents/skills/); add --scope user for a personal install.
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .agents/skills && cp -r skills-src/vivado-impl .agents/skills/vivado-impl && rm -rf skills-srcUse ~/.agents/skills/ instead of .agents/skills for a personal install.
Codex skills documentation · loads skills from .agents/skills/
Install the "vivado-impl" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-impl into .agents/skills/vivado-impl/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-impl", then confirm the skill loads.Codex copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a cursorProject install goes to .agents/skills/; add -g for ~/.cursor/skills/.
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-impl --agent cursorProject scope by default (.agents/skills/); add --scope user for a personal install.
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .cursor/skills && cp -r skills-src/vivado-impl .cursor/skills/vivado-impl && rm -rf skills-srcUse ~/.cursor/skills/ instead of .cursor/skills for a personal install.
Cursor skills documentation · loads skills from .cursor/skills/, .agents/skills/, .claude/skills/, .codex/skills/
Install the "vivado-impl" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-impl into .cursor/skills/vivado-impl/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-impl", then confirm the skill loads.Cursor copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.
$ gemini skills install https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git --path vivado-impl--scope user (default) or --scope workspace; --path is the subfolder of the repo that holds the skill; --consent skips the security confirmation prompt.
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a gemini-cliProject install goes to .agents/skills/; add -g for ~/.gemini/skills/.
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-impl --agent gemini-cliProject scope by default (.agents/skills/); add --scope user for a personal install.
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .gemini/skills && cp -r skills-src/vivado-impl .gemini/skills/vivado-impl && rm -rf skills-srcUse ~/.gemini/skills/ instead of .gemini/skills for a personal install, then run /skills reload.
Gemini CLI skills documentation · loads skills from .gemini/skills/, .agents/skills/
Install the "vivado-impl" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-impl into .gemini/skills/vivado-impl/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-impl", then confirm the skill loads.Gemini CLI copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-implInstalls for Copilot at project scope by default; add --scope user for a personal install. Preview a skill first with gh skill preview. Needs GitHub CLI 2.90.0 or later (public preview).
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a github-copilotProject install goes to .agents/skills/; add -g for ~/.copilot/skills/.
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .github/skills && cp -r skills-src/vivado-impl .github/skills/vivado-impl && rm -rf skills-srcUse ~/.copilot/skills/ instead of .github/skills for a personal install. Commit .github/skills so cloud agent and code review can use it.
GitHub Copilot skills documentation · loads skills from .github/skills/, .claude/skills/, .agents/skills/
Install the "vivado-impl" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-impl into .github/skills/vivado-impl/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-impl", then confirm the skill loads.GitHub Copilot copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a opencodeOpenCode documents no install command of its own. Project install goes to .agents/skills/; add -g for ~/.config/opencode/skills/.
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-impl --agent opencodeProject scope by default (.agents/skills/); add --scope user for a personal install.
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .opencode/skills && cp -r skills-src/vivado-impl .opencode/skills/vivado-impl && rm -rf skills-srcUse ~/.config/opencode/skills/ instead of .opencode/skills for a personal install.
OpenCode skills documentation · loads skills from .opencode/skills/, .claude/skills/, .agents/skills/
Install the "vivado-impl" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-impl into .opencode/skills/vivado-impl/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-impl", then confirm the skill loads.OpenCode copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.
vivado-implA skill your agent uses when the user needs Vivado implementation strategy selection or optimization.
Vivado Impl is an agent skill from Shinei-Nouzen-Arch/FPGA-Agent. Use this skill when the user needs Vivado implementation strategy selection or optimization. Covers optdesign, poweroptdesign, placedesign, physoptdesign, routedesign, implementation directives/options, congestion-driven placement, fanout/placement/routing/SLR/register physical optimization, hold fixing, incremental implementation, ECO flow, and implementation run strategies for performance, congestion, area, and power. This skill chooses implementation-phase tactics and tradeoffs. For TCL command…
Its SKILL.md is about 3.7k tokens, which your agent loads only when the skill is triggered. The skill folder holds 20 other files (for example `REFERENCE.md` and `agents/openai.yaml`).
It sits in Agent Workflows, covering Task breakdown. The licence is GPL-2.0.
5 steps, taken from the first numbered list in SKILL.md.
Read from SKILL.md and the folder at commit b60a52e. It shows what the files ask for, not the result of running them.
Pre-approves nothing: there is no allowed-tools line, so your agent's usual permission prompts apply.
From allowed-tools in the SKILL.md frontmatter.
No scripts in the folder and no shell commands in SKILL.md (its code samples are tcl).
From the folder's file list and the shell code blocks in SKILL.md.
No URLs in SKILL.md.
From URLs in SKILL.md, links to its own repository left out.
Names no API keys, tokens, secrets or passwords.
From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.
Vivado Impl loads about 3.7k tokens when it runs. Until then it costs about 184 tokens; SKILL.md has 1,183 words of instructions outside code blocks.
Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.
The automated check found no risky patterns in SKILL.md.
Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.
The full file from Shinei-Nouzen-Arch/FPGA-Agent at commit b60a52e, republished under its GPL-2.0 licence (© Shinei-Nouzen-Arch). 1,183 words, ~3,671 tokens.
.claude/skills/vivado-impl/SKILL.md (or your agent's skills folder). This skill also uses 8 other files; get the full folder from GitHub.Based on UG904 (v2025.2). For command syntax and property tables see REFERENCE.md; for report_qor_suggestions RTL optimization examples (UG906 before/after) see examples/ug906/ directory.
opt_design ← Logic optimization (REQUIRED)
↓
power_opt_design ← Clock gating power opt (OPTIONAL, not Versal)
↓
place_design ← Placement (REQUIRED)
↓
power_opt_design ← Post-place power opt (OPTIONAL)
↓
phys_opt_design ← Post-place physical opt (OPTIONAL, recommended)
↓
route_design ← Routing (REQUIRED)
↓
phys_opt_design ← Post-route physical opt (OPTIONAL)
↓
write_bitstream ← Bitstream (all except Versal)
write_device_image ← Device image (Versal only)Key rule: All implementation commands are re-entrant — they can be run repeatedly on the same design. Each run optimizes the results of the previous run.
| Scenario | Directive | Effect |
|---|---|---|
| Default / first try | Default | Default optimization phases |
| Deep exploration | Explore | Multiple passes of optimization |
| Area reduction (comb) | ExploreArea | Multiple passes, emphasis on reducing combinational logic |
| Area reduction (comb+seq) | ExploreSequentialArea | Reduces both combinational and sequential logic |
| Explore + LUT remap | ExploreWithRemap | Explore + Remap optimization |
| Fast iteration | RuntimeOptimized | Minimal optimization passes |
| QoR-suggested | RQS | Uses report_qor_suggestion strategy |
| Phase | Option | Default | Description |
|---|---|---|---|
| 1 | -retarget | ON | Retarget primitives across device families |
| 2 | -propconst | ON | Constant propagation |
| 3 | -sweep | ON | Remove loadless cells, tie-off, retarget dual-port→single-port RAM |
| 4 | -muxf_remap | off | Remap MUXF7/F8/F9 to LUT3 for routability |
| 5 | -carry_remap | off | Remap short CARRY chains to LUTs |
| 6 | -control_set_merge | off | Merge equivalent control set drivers |
| 7 | -merge_equivalent_drivers | off | Merge all equivalent drivers (not just control) |
| 8 | -bufg_opt | ON | Insert BUFG on high-fanout clock/non-clock nets |
| 9 | -shift_register_opt | ON | SRL fanout opt + SRL↔register transforms |
| 10 | -mbufg_opt | off | Replace parallel BUFGCEs with MBUFG (Versal) |
| 11 | -dsp_register_opt | off | Optimize DSP pipeline registers |
| 12 | (auto) | ON | Control Set Reduction (CONTROL_SET_REMAP property) |
| 13 | -hier_fanout_limit <N> | off | Module-based fanout replication |
| 13 | -control_set_opt | off | Control Set Optimization (auto-selected candidates) |
| 14 | -remap | off | Combine cascaded LUTs to reduce logic levels |
| 15 | -resynth_remap | off | Timing-driven re-synthesis + remap |
| 16 | -resynth_area | off | Re-synthesis for area (reduce LUTs) |
| 17 | -resynth_seq_area | off | Re-synthesis for area (comb + sequential) |
| 18 | -bram_power_opt | ON | Block RAM power optimization (WRITE_MODE) |
IMPORTANT: Specifying individual options disables ALL default options. To run defaults + extras: opt_design -retarget -propconst -sweep -bufg_opt -shift_register_opt -bram_power_opt -remap
| Scenario | Directive | Designs Benefited |
|---|---|---|
| Default | Default | All |
| Deep exploration | Explore | All (higher effort detail placement) |
| Aggressive exploration | AggressiveExplore | Timing-critical designs |
| RAM/DSP dense | WLDrivenBlockPlacement | Many BRAM/DSP blocks |
| RAM/DSP dense | EarlyBlockPlacement | RAM/DSP as placement anchors |
| Timing meets post-place but fails post-route | ExtraNetDelay_high | Long-distance nets, high fanout |
| Timing meets post-place but fails post-route | ExtraNetDelay_low | Same, lower pessimism |
| Congestion | AltSpreadLogic_high | High connectivity → congestion |
| Congestion (moderate) | AltSpreadLogic_medium/low | Moderate congestion |
| SSI congestion | SSI_SpreadLogic_high/low | SSI devices |
| SSI SLR balancing | SSI_SpreadSLLs | Balance SLL connections across SLRs |
| SSI SLR balancing | SSI_BalanceSLLs | Balance SLLs between SLRs |
| SSI SLR balancing | SSI_BalanceSLRs | Balance cell count between SLRs |
| SSI high utilization | SSI_HighUtilSLRs | Pack logic closer in each SLR |
| Extra post-place opt | ExtraPostPlacementOpt | All |
| Alternate timing | ExtraTimingOpt | Alternative timing-driven algorithms |
| ML-predicted best | Auto_1 | Highest confidence ML prediction |
| ML-predicted 2nd | Auto_2 | Second best ML prediction |
| ML-predicted 3rd | Auto_3 | Third best ML prediction |
| Fast iteration | RuntimeOptimized | Trade QoR for speed |
| Fastest | Quick | Non-timing-driven, minimum legal placement |
| QoR-suggested | RQS | Uses report_qor_suggestion |
| Option | Effect |
|---|---|
-post_place_opt | Extra timing optimization after placement |
-timing_summary | Force STA-based timing summary (more accurate, slower) |
-no_timing_driven | Wirelength-only placement (fastest) |
-no_psip | Disable Physical Synthesis in Placer |
-no_bufg_opt | Disable BUFG insertion during placement |
-sll_align_opt | Align SLL registers for SSI multi-die parts |
-ultrathreads | Parallel placement across SLRs (UltraScale+ SSI) |
-unplace | Remove all non-fixed placements |
TIP: Post-route phys_opt is most effective on designs with few failing paths (WNS > -0.200 ns). Designs with > 200 failing endpoints see little improvement.
| Scenario | Directive | Effect |
|---|---|---|
| Default | Default | Default optimizations |
| Deep exploration | Explore | Multi-pass + SLR crossing + critical path final phase |
| Explore + hold fix | ExploreWithHoldFix | Explore + hold violation fixing |
| Explore + aggressive hold | ExploreWithAggressiveHoldFix | Explore + aggressive hold fixing |
| Most aggressive | AggressiveExplore | Allows WNS degradation in SLR crossing opt |
| Alternative replication | AlternateReplication | Different critical cell replication algorithm |
| Fanout-focused | AggressiveFanoutOpt | Aggressive fanout optimization |
| Add retiming | AddRetime | Default flow + register retiming |
| Aggressive + retiming | AlternateFlowWithRetiming | Aggressive replication + DSP/BRAM opt + retiming |
| Fast | RuntimeOptimized | Fewest iterations |
Setup optimization (post-place defaults):
| Option | Description |
|---|---|
-fanout_opt | Replicate high-fanout net drivers (default post-place) |
-critical_cell_opt | Replicate cells in failing paths (default post-place) |
-placement_opt | Re-place critical path cells (default both modes) |
-dsp_register_opt | Move registers in/out of DSP cells |
-bram_register_opt | Move registers in/out of BRAM cells |
-uram_register_opt | Move registers in/out of UltraRAM cells |
-shift_register_opt | Extract SRL end stages to improve timing |
-restruct_opt | Swap LUT connections to reduce logic levels |
-lut_opt | Single LUT movement/replication |
-clock_opt | Useful clock skew optimization |
Routing optimization (post-route defaults):
| Option | Description |
|---|---|
-routing_opt | Re-route critical nets/pins (default post-route) |
-slr_crossing_opt | Optimize inter-SLR paths (default both modes) |
-critical_pin_opt | Remap LUT pins to faster physical pins |
Hold fixing:
| Option | Description |
|---|---|
-hold_fix | Fix hold violations above threshold |
-aggressive_hold_fix | Fix more hold violations |
-sll_reg_hold_fix | SLL register hold fix (UltraScale+) |
-insert_negative_edge_ffs | Insert neg-edge FFs to split hold paths |
Other:
| Option | Description |
|---|---|
-retime | Register retiming (Versal) |
-interconnect_retime | Interconnect retiming by FF movement (Versal) |
-force_replication_on_nets <nets> | Force driver replication on specific nets |
-equ_drivers_opt | Rewire loads to equivalent drivers |
-casc_opt | LUT cascade optimization (Versal) |
-cell_group_opt | Critical fanin cone group opt (Versal) |
-bram_enable_opt | Reverse BRAM power opt on timing-critical enable paths |
-path_groups <args> | Limit optimization to specific path groups |
-tns_cleanup | Allow slack degradation if WNS maintained (with -slr_crossing_opt) |
| Scenario | Directive | Effect |
|---|---|---|
| Default | Default | Default routing |
| Explore alternatives | Explore | Explore different critical path routes (signoff timing) |
| Aggressive exploration | AggressiveExplore | More aggressive thresholds |
| No timing relaxation | NoTimingRelaxation | Never relax timing goals |
| More iterations | MoreGlobalIterations | Detailed timing analysis all stages |
| Emphasize delay | HigherDelayCost | Trade compile time for delay optimization |
| Fast | RuntimeOptimized | Fewest iterations |
| Congestion | AlternateCLBRouting | Alternate CLB routing algorithms |
| Fastest | Quick | Non-timing-driven, minimum legal routing |
| QoR-suggested | RQS | Uses report_qor_suggestion |
| Option | Effect |
|---|---|
-tns_cleanup | Focus on WNS, fix non-critical failing paths. Use before post-route phys_opt |
-preserve | Preserve existing routes, route remaining. For pre-routing critical nets |
-nets <net_objects> | Route only specified nets |
-pins <pin_objects> | Route only specified pins |
-delay | Route individual nets with smallest delay |
-auto_delay | Route with timing-constraint-driven budgets (use with -nets/-pins) |
-max_delay <ps> / -min_delay <ps> | Target delay for pin routing (use with -pins) |
-unroute | Remove routing (entire design or specific nets/pins) |
-timing_summary | Force STA timing summary (more accurate) |
-finalize | Complete partially routed connections (ECO flow) |
-eco | Incremental ECO routing (faster after small changes) |
-ultrathreads | Parallel routing (faster, slight variation between runs) |
-no_timing_driven | Disable timing-driven routing (feasibility test only) |
# Route top 10 critical nets first with minimum delay
set preRoutes [get_nets -of [get_timing_paths -max_paths 10]]
route_design -nets [get_nets $preRoutes] -delay
# Then route rest preserving critical routes
route_design -preserve# Basic usage (optimize entire design)
power_opt_design
# Control scope
set_power_opt -include_cells [get_cells inst_A]
set_power_opt -exclude_cells [get_cells inst_B]
set_power_opt -cell_types {BRAM}
set_power_opt -clocks {clk1}Note: Not supported for Versal. BRAM power opt is skipped if already done by opt_design.
# Non-Project Mode
read_checkpoint -incremental <reference_routed.dcp>
# Automatic incremental (recommended)
read_checkpoint -incremental -auto_incremental <reference.dcp>
# Force incremental even if criteria not met
read_checkpoint -incremental -force_incr <reference.dcp>
# Fix specific objects
read_checkpoint -incremental <ref.dcp> -fix_objects [all_rams]read_checkpoint -incremental -directive <directive> <ref.dcp>| Directive | Effect |
|---|---|
RuntimeOptimized | Reuse max, target same WNS as reference (default) |
TimingClosure | Rip up failing paths, try harder to close timing |
Quick | No timer, fastest, needs WNS > 1.0 ns |
report_incremental_reuse -file incr_reuse.rptNote: Not supported for Versal.
report_design_analysis -congestion -file congestion.rpt
report_route_status -file route_status.rptAlternateRoutability directive, reduce MUXF/CARRY usage-muxf_remap, -carry_remap, LUT_DECOMPOSE propertyAltSpreadLogic_high or SSI_SpreadLogic_highAlternateCLBRoutingPerformance_Auto_1/2/3, Performance_Explore, Performance_ExplorePostRoutePhysOpt, Performance_ExploreWithRemap, Performance_WLBlockPlacement, Performance_WLBlockPlacementFanoutOpt, Performance_EarlyBlockPlacement, Performance_NetDelay_high/low, Performance_Retiming, Performance_ExtraTimingOpt, Performance_RefinePlacement, Performance_SpreadSLLs, Performance_BalanceSLLs, Performance_BalanceSLRs, Performance_HighUtilSLRs
Congestion_SpreadLogic_high/medium/low, Congestion_SSI_SpreadLogic_high/low
Area_Explore, Area_ExploreSequential, Area_ExploreWithRemap
© Shinei-Nouzen-Arch, GPL-2.0. Rendered from Markdown: HTML in the file is shown as text, images as links, and headings moved down two levels. Raw file
SKILL.md and 8 other files in vivado-impl of Shinei-Nouzen-Arch/FPGA-Agent.
Open the folder on GitHubat commit b60a52e
Vivado Impl next to the 5 skills that share the most tags, products or categories with it. Stars are the repository's; “used in” counts other GitHub owners with a copy.
| Skill | Stars | Used in | Tokens | Auto-check | Licence | Repo updated |
|---|---|---|---|---|---|---|
| Vivado Impl this skillShinei-Nouzen-Arch/FPGA-Agent | 180 | — | ~3.7k | Automated safety check: Pass | GPL-2.0 | |
| MemPalace Task HandoffMemPalace/mempalace | 60k | — | ~1.9k | Automated safety check: Pass | MIT | |
| Planning And Task Breakdownabashev/vfs-s3 | 106 | 8 repos | ~1.9k | Automated safety check: Pass | Apache-2.0 | |
| Incremental Implementationaddyosmani/agent-skills | 105k | 1 repos | ~2.3k | Automated safety check: Pass | MIT | |
| ULW Plan Workflowcode-yeongyu/oh-my-openagent | 70k | — | ~3.9k | Automated safety check: Pass | Custom licence | |
| Ask NavigatorYeachan-Heo/oh-my-claudecode | 40k | — | ~4.1k | Automated safety check: Pass | MIT |
MemPalace/mempalace
Creates, hands off, claims, executes and closes agent tasks through the MemPalace logstream, with approval of the exact task before it is recorded.
abashev/vfs-s3
Breaks work into ordered tasks. An agent skill from abashev/vfs-s3.
addyosmani/agent-skills
Delivers a change in thin vertical slices, each implemented, tested, verified and committed before the next, using vertical, contract-first or risk-first slicing.
code-yeongyu/oh-my-openagent
Explore-first planning that turns a vague or large request into one decision-complete work plan, written only after your approval and executed by a separate worker.
Yeachan-Heo/oh-my-claudecode
Charts a foggy effort into a map of decision tickets on the repo's issue tracker and works through them one per session, producing decisions rather than deliverables.
tailcallhq/forgecode
Writes a structured Markdown implementation plan with checkbox tasks, verification criteria and risks, then checks it with a validation script; no code changes.
Shinei-Nouzen-Arch/FPGA-Agent
A skill your agent uses when the user needs help with Vivado in-system debugging, hardware programming, or debug core configuration.
Shinei-Nouzen-Arch/FPGA-Agent
A skill your agent uses when the user needs Vivado design analysis, timing report interpretation, or timing-closure diagnosis.
Shinei-Nouzen-Arch/FPGA-Agent
A skill your agent uses when the user needs help writing XDC/SDC timing or physical constraints for Vivado FPGA designs.
Shinei-Nouzen-Arch/FPGA-Agent
A skill your agent uses when the user needs help with Vivado simulation strategy, flow selection, and debugging.
Shinei-Nouzen-Arch/FPGA-Agent
A skill your agent uses when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synthdesign option tuning, resource inference control…
Shinei-Nouzen-Arch/FPGA-Agent
Generate, review, explain, and execute Vivado/Vitis TCL scripts for FPGA design flows, and verify their execution results.
Categories
A skill your agent uses when the user needs Vivado implementation strategy selection or optimization. Vivado Impl is an agent skill from Shinei-Nouzen-Arch/FPGA-Agent. Use this skill when the user needs Vivado implementation strategy selection or optimization.
Vivado Impl fits situations like: the user needs Vivado implementation strategy selection; tasks that involve Task breakdown.
Run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a claude-code`. Or copy the skill folder (vivado-impl in Shinei-Nouzen-Arch/FPGA-Agent) into .claude/skills/vivado-impl in your project. Claude Code loads it when a task matches its description.
Run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a codex`. Or copy the skill folder (vivado-impl in Shinei-Nouzen-Arch/FPGA-Agent) into .agents/skills/vivado-impl in your project. Codex loads it when a task matches its description.
Cursor, Gemini CLI, GitHub Copilot and OpenCode also load SKILL.md folders. With the skills CLI, run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a cursor` (or -a gemini-cli, github-copilot or opencode for the others). To copy it by hand, put the folder in .cursor/skills/vivado-impl, .gemini/skills/vivado-impl, .github/skills/vivado-impl and .opencode/skills/vivado-impl in your project.
SKILL.md names no scripts, command-line tools or credentials: Vivado Impl is instructions for the agent only.
SKILL.md contains no URLs. Any network use would come from the scripts or tools the agent runs. This is read from the text; nothing was executed.
Our automated static check of SKILL.md found no risky patterns, such as piping downloads into a shell, reading credential files or hidden Unicode. It is not a guarantee. Review the folder before installing.
Vivado Impl is published under the GPL-2.0 licence (the repository's licence). It allows redistribution, so the full SKILL.md is shown on this page.
About 3.7k tokens (SKILL.md is roughly 15k characters). Agents keep only the skill's name and description in context until a task matches; then they load SKILL.md in full.
Skills that share tags, products or a category with Vivado Impl: MemPalace Task Handoff (MemPalace/mempalace, 60k stars), Planning And Task Breakdown (abashev/vfs-s3, 106 stars), Incremental Implementation (addyosmani/agent-skills, 105k stars) and ULW Plan Workflow (code-yeongyu/oh-my-openagent, 70k stars). The comparison table on this page puts their stars, adoption, token cost, safety result and licence side by side.
Shinei-Nouzen-Arch (a GitHub user) maintains it in Shinei-Nouzen-Arch/FPGA-Agent, which has 180 GitHub stars. The repository holds 10 skills in this directory. The repository was last updated on September 5, 2026.
Source: Shinei-Nouzen-Arch/FPGA-Agent on GitHub. Facts on this page come from the repository at the commit we read; the author's words are quoted as theirs.