A skill your agent uses when the user needs Vivado implementation strategy selection or optimization.

GPL-2.0Auto-check passedAgent Workflows

Install Vivado Impl

skills CLI
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a claude-code

Project install by default; add -g for ~/.claude/skills/.

GitHub CLI
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-impl --agent claude-code

Project scope by default; add --scope user for a personal install. Needs GitHub CLI 2.90.0 or later (public preview).

Manual copy
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .claude/skills && cp -r skills-src/vivado-impl .claude/skills/vivado-impl && rm -rf skills-src

Use ~/.claude/skills/ instead of .claude/skills for a personal install. The folder must contain SKILL.md.

Claude Code skills documentation · loads skills from .claude/skills/

Facts

Skill name
vivado-impl
GitHub stars
180
Token cost
~3.7k tokens
SKILL.md length
1,183 words
Files
9
Skills in repo
10
Repo updated
First seen
Licence
GPL-2.0

At a glance

A skill your agent uses when the user needs Vivado implementation strategy selection or optimization.

  • Works in 5 steps: Synthesis: Use AlternateRoutability… → opt_design: Use -muxf_remap,… → place_design: Use AltSpreadLogic_high or… → …
  • The user needs Vivado implementation strategy selection
  • SKILL.md covers Implementation Flow Overview, opt_design — Logic Optimization, place_design — Placement and phys_opt_design — Physical…, plus 5 more sections
  • Instructions only: no scripts, shell commands, URLs or credentials in SKILL.md

What it does

Vivado Impl is an agent skill from Shinei-Nouzen-Arch/FPGA-Agent. Use this skill when the user needs Vivado implementation strategy selection or optimization. Covers optdesign, poweroptdesign, placedesign, physoptdesign, routedesign, implementation directives/options, congestion-driven placement, fanout/placement/routing/SLR/register physical optimization, hold fixing, incremental implementation, ECO flow, and implementation run strategies for performance, congestion, area, and power. This skill chooses implementation-phase tactics and tradeoffs. For TCL command…

Its SKILL.md is about 3.7k tokens, which your agent loads only when the skill is triggered. The skill folder holds 20 other files (for example `REFERENCE.md` and `agents/openai.yaml`).

It sits in Agent Workflows, covering Task breakdown. The licence is GPL-2.0.

When your agent uses it

  • The user needs Vivado implementation strategy selection
  • Tasks that involve Task breakdown

Example prompts

  • “/vivado-impl”

Workflow steps

5 steps, taken from the first numbered list in SKILL.md.

  1. Synthesis: Use AlternateRoutability directive, reduce MUXF/CARRY usage
  2. opt_design: Use -muxf_remap, -carry_remap, LUT_DECOMPOSE property
  3. place_design: Use AltSpreadLogic_high or SSI_SpreadLogic_high
  4. route_design: Use AlternateCLBRouting
  5. RTL changes: Reduce fanout, pipeline long paths, reduce resource utilization

What it can do on your machine

Read from SKILL.md and the folder at commit b60a52e. It shows what the files ask for, not the result of running them.

  • Tool permissions

    Pre-approves nothing: there is no allowed-tools line, so your agent's usual permission prompts apply.

    From allowed-tools in the SKILL.md frontmatter.

  • Runs code

    No scripts in the folder and no shell commands in SKILL.md (its code samples are tcl).

    From the folder's file list and the shell code blocks in SKILL.md.

  • Network

    No URLs in SKILL.md.

    From URLs in SKILL.md, links to its own repository left out.

  • Credentials

    Names no API keys, tokens, secrets or passwords.

    From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.

Context cost

Vivado Impl loads about 3.7k tokens when it runs. Until then it costs about 184 tokens; SKILL.md has 1,183 words of instructions outside code blocks.

Always · name and description, kept in context so the agent knows when to use it
~184
When it runs · the whole SKILL.md, loaded when a task matches
~3.7k

Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.

Safety

Auto-check passed

The automated check found no risky patterns in SKILL.md.

Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.

SKILL.md

The full file from Shinei-Nouzen-Arch/FPGA-Agent at commit b60a52e, republished under its GPL-2.0 licence (© Shinei-Nouzen-Arch). 1,183 words, ~3,671 tokens.

Download SKILL.mdSave it as .claude/skills/vivado-impl/SKILL.md (or your agent's skills folder). This skill also uses 8 other files; get the full folder from GitHub.
name
vivado-impl
description
Use this skill when the user needs Vivado implementation strategy selection or optimization. Covers opt_design, power_opt_design, place_design, phys_opt_design, route_design, implementation directives/options, congestion-driven placement, fanout/placement/routing/SLR/register physical optimization, hold fixing, incremental implementation, ECO flow, and implementation run strategies for performance, congestion, area, and power. This skill chooses implementation-phase tactics and tradeoffs. For TCL command generation/execution use vivado-tcl, for synthesis use vivado-synth, for constraints use vivado-constraints, for report interpretation use vivado-analysis, for end-to-end timing closure use vivado-timing-closure.

Vivado Implementation Decision Guide

Based on UG904 (v2025.2). For command syntax and property tables see REFERENCE.md; for report_qor_suggestions RTL optimization examples (UG906 before/after) see examples/ug906/ directory.

Implementation Flow Overview

opt_design          ← Logic optimization (REQUIRED)
  ↓
power_opt_design    ← Clock gating power opt (OPTIONAL, not Versal)
  ↓
place_design        ← Placement (REQUIRED)
  ↓
power_opt_design    ← Post-place power opt (OPTIONAL)
  ↓
phys_opt_design     ← Post-place physical opt (OPTIONAL, recommended)
  ↓
route_design        ← Routing (REQUIRED)
  ↓
phys_opt_design     ← Post-route physical opt (OPTIONAL)
  ↓
write_bitstream     ← Bitstream (all except Versal)
write_device_image  ← Device image (Versal only)

Key rule: All implementation commands are re-entrant — they can be run repeatedly on the same design. Each run optimizes the results of the previous run.


opt_design — Logic Optimization

Directive Decision Table
ScenarioDirectiveEffect
Default / first tryDefaultDefault optimization phases
Deep explorationExploreMultiple passes of optimization
Area reduction (comb)ExploreAreaMultiple passes, emphasis on reducing combinational logic
Area reduction (comb+seq)ExploreSequentialAreaReduces both combinational and sequential logic
Explore + LUT remapExploreWithRemapExplore + Remap optimization
Fast iterationRuntimeOptimizedMinimal optimization passes
QoR-suggestedRQSUses report_qor_suggestion strategy
Available Optimizations (18 phases)
PhaseOptionDefaultDescription
1-retargetONRetarget primitives across device families
2-propconstONConstant propagation
3-sweepONRemove loadless cells, tie-off, retarget dual-port→single-port RAM
4-muxf_remapoffRemap MUXF7/F8/F9 to LUT3 for routability
5-carry_remapoffRemap short CARRY chains to LUTs
6-control_set_mergeoffMerge equivalent control set drivers
7-merge_equivalent_driversoffMerge all equivalent drivers (not just control)
8-bufg_optONInsert BUFG on high-fanout clock/non-clock nets
9-shift_register_optONSRL fanout opt + SRL↔register transforms
10-mbufg_optoffReplace parallel BUFGCEs with MBUFG (Versal)
11-dsp_register_optoffOptimize DSP pipeline registers
12(auto)ONControl Set Reduction (CONTROL_SET_REMAP property)
13-hier_fanout_limit <N>offModule-based fanout replication
13-control_set_optoffControl Set Optimization (auto-selected candidates)
14-remapoffCombine cascaded LUTs to reduce logic levels
15-resynth_remapoffTiming-driven re-synthesis + remap
16-resynth_areaoffRe-synthesis for area (reduce LUTs)
17-resynth_seq_areaoffRe-synthesis for area (comb + sequential)
18-bram_power_optONBlock RAM power optimization (WRITE_MODE)

IMPORTANT: Specifying individual options disables ALL default options. To run defaults + extras: opt_design -retarget -propconst -sweep -bufg_opt -shift_register_opt -bram_power_opt -remap


place_design — Placement

Directive Decision Table
ScenarioDirectiveDesigns Benefited
DefaultDefaultAll
Deep explorationExploreAll (higher effort detail placement)
Aggressive explorationAggressiveExploreTiming-critical designs
RAM/DSP denseWLDrivenBlockPlacementMany BRAM/DSP blocks
RAM/DSP denseEarlyBlockPlacementRAM/DSP as placement anchors
Timing meets post-place but fails post-routeExtraNetDelay_highLong-distance nets, high fanout
Timing meets post-place but fails post-routeExtraNetDelay_lowSame, lower pessimism
CongestionAltSpreadLogic_highHigh connectivity → congestion
Congestion (moderate)AltSpreadLogic_medium/lowModerate congestion
SSI congestionSSI_SpreadLogic_high/lowSSI devices
SSI SLR balancingSSI_SpreadSLLsBalance SLL connections across SLRs
SSI SLR balancingSSI_BalanceSLLsBalance SLLs between SLRs
SSI SLR balancingSSI_BalanceSLRsBalance cell count between SLRs
SSI high utilizationSSI_HighUtilSLRsPack logic closer in each SLR
Extra post-place optExtraPostPlacementOptAll
Alternate timingExtraTimingOptAlternative timing-driven algorithms
ML-predicted bestAuto_1Highest confidence ML prediction
ML-predicted 2ndAuto_2Second best ML prediction
ML-predicted 3rdAuto_3Third best ML prediction
Fast iterationRuntimeOptimizedTrade QoR for speed
FastestQuickNon-timing-driven, minimum legal placement
QoR-suggestedRQSUses report_qor_suggestion
Key Options
OptionEffect
-post_place_optExtra timing optimization after placement
-timing_summaryForce STA-based timing summary (more accurate, slower)
-no_timing_drivenWirelength-only placement (fastest)
-no_psipDisable Physical Synthesis in Placer
-no_bufg_optDisable BUFG insertion during placement
-sll_align_optAlign SLL registers for SSI multi-die parts
-ultrathreadsParallel placement across SLRs (UltraScale+ SSI)
-unplaceRemove all non-fixed placements

phys_opt_design — Physical Optimization

Two Modes
  • Post-place: More aggressive, based on placement timing estimates
  • Post-route: More conservative, uses actual routed delays, auto-updates routing

TIP: Post-route phys_opt is most effective on designs with few failing paths (WNS > -0.200 ns). Designs with > 200 failing endpoints see little improvement.

Directive Decision Table
ScenarioDirectiveEffect
DefaultDefaultDefault optimizations
Deep explorationExploreMulti-pass + SLR crossing + critical path final phase
Explore + hold fixExploreWithHoldFixExplore + hold violation fixing
Explore + aggressive holdExploreWithAggressiveHoldFixExplore + aggressive hold fixing
Most aggressiveAggressiveExploreAllows WNS degradation in SLR crossing opt
Alternative replicationAlternateReplicationDifferent critical cell replication algorithm
Fanout-focusedAggressiveFanoutOptAggressive fanout optimization
Add retimingAddRetimeDefault flow + register retiming
Aggressive + retimingAlternateFlowWithRetimingAggressive replication + DSP/BRAM opt + retiming
FastRuntimeOptimizedFewest iterations
Show full SKILL.md (548 more words)Show less
Key Individual Options

Setup optimization (post-place defaults):

OptionDescription
-fanout_optReplicate high-fanout net drivers (default post-place)
-critical_cell_optReplicate cells in failing paths (default post-place)
-placement_optRe-place critical path cells (default both modes)
-dsp_register_optMove registers in/out of DSP cells
-bram_register_optMove registers in/out of BRAM cells
-uram_register_optMove registers in/out of UltraRAM cells
-shift_register_optExtract SRL end stages to improve timing
-restruct_optSwap LUT connections to reduce logic levels
-lut_optSingle LUT movement/replication
-clock_optUseful clock skew optimization

Routing optimization (post-route defaults):

OptionDescription
-routing_optRe-route critical nets/pins (default post-route)
-slr_crossing_optOptimize inter-SLR paths (default both modes)
-critical_pin_optRemap LUT pins to faster physical pins

Hold fixing:

OptionDescription
-hold_fixFix hold violations above threshold
-aggressive_hold_fixFix more hold violations
-sll_reg_hold_fixSLL register hold fix (UltraScale+)
-insert_negative_edge_ffsInsert neg-edge FFs to split hold paths

Other:

OptionDescription
-retimeRegister retiming (Versal)
-interconnect_retimeInterconnect retiming by FF movement (Versal)
-force_replication_on_nets <nets>Force driver replication on specific nets
-equ_drivers_optRewire loads to equivalent drivers
-casc_optLUT cascade optimization (Versal)
-cell_group_optCritical fanin cone group opt (Versal)
-bram_enable_optReverse BRAM power opt on timing-critical enable paths
-path_groups <args>Limit optimization to specific path groups
-tns_cleanupAllow slack degradation if WNS maintained (with -slr_crossing_opt)

route_design — Routing

Directive Decision Table
ScenarioDirectiveEffect
DefaultDefaultDefault routing
Explore alternativesExploreExplore different critical path routes (signoff timing)
Aggressive explorationAggressiveExploreMore aggressive thresholds
No timing relaxationNoTimingRelaxationNever relax timing goals
More iterationsMoreGlobalIterationsDetailed timing analysis all stages
Emphasize delayHigherDelayCostTrade compile time for delay optimization
FastRuntimeOptimizedFewest iterations
CongestionAlternateCLBRoutingAlternate CLB routing algorithms
FastestQuickNon-timing-driven, minimum legal routing
QoR-suggestedRQSUses report_qor_suggestion
Key Options
OptionEffect
-tns_cleanupFocus on WNS, fix non-critical failing paths. Use before post-route phys_opt
-preservePreserve existing routes, route remaining. For pre-routing critical nets
-nets <net_objects>Route only specified nets
-pins <pin_objects>Route only specified pins
-delayRoute individual nets with smallest delay
-auto_delayRoute with timing-constraint-driven budgets (use with -nets/-pins)
-max_delay <ps> / -min_delay <ps>Target delay for pin routing (use with -pins)
-unrouteRemove routing (entire design or specific nets/pins)
-timing_summaryForce STA timing summary (more accurate)
-finalizeComplete partially routed connections (ECO flow)
-ecoIncremental ECO routing (faster after small changes)
-ultrathreadsParallel routing (faster, slight variation between runs)
-no_timing_drivenDisable timing-driven routing (feasibility test only)
Pre-routing Critical Nets Pattern
tcl
# Route top 10 critical nets first with minimum delay
set preRoutes [get_nets -of [get_timing_paths -max_paths 10]]
route_design -nets [get_nets $preRoutes] -delay
# Then route rest preserving critical routes
route_design -preserve

power_opt_design — Power Optimization

tcl
# Basic usage (optimize entire design)
power_opt_design

# Control scope
set_power_opt -include_cells [get_cells inst_A]
set_power_opt -exclude_cells [get_cells inst_B]
set_power_opt -cell_types {BRAM}
set_power_opt -clocks {clk1}

Note: Not supported for Versal. BRAM power opt is skipped if already done by opt_design.


Incremental Implementation

Setup
tcl
# Non-Project Mode
read_checkpoint -incremental <reference_routed.dcp>
# Automatic incremental (recommended)
read_checkpoint -incremental -auto_incremental <reference.dcp>
# Force incremental even if criteria not met
read_checkpoint -incremental -force_incr <reference.dcp>
# Fix specific objects
read_checkpoint -incremental <ref.dcp> -fix_objects [all_rams]
Incremental Directives
tcl
read_checkpoint -incremental -directive <directive> <ref.dcp>
DirectiveEffect
RuntimeOptimizedReuse max, target same WNS as reference (default)
TimingClosureRip up failing paths, try harder to close timing
QuickNo timer, fastest, needs WNS > 1.0 ns
Auto Incremental Criteria
  • Cell matching ≥ 94%
  • Net matching ≥ 90%
  • Reference WNS ≥ -0.250 ns
Analysis
tcl
report_incremental_reuse -file incr_reuse.rpt

Note: Not supported for Versal.


Congestion Analysis & Resolution

Congestion Levels
  • Level 5 (32x32 tiles) — warning threshold, expect timing impact
  • Level 8+ — router early exit, design likely unroutable
Diagnosis
tcl
report_design_analysis -congestion -file congestion.rpt
report_route_status -file route_status.rpt
Resolution Decision Tree
  1. Synthesis: Use AlternateRoutability directive, reduce MUXF/CARRY usage
  2. opt_design: Use -muxf_remap, -carry_remap, LUT_DECOMPOSE property
  3. place_design: Use AltSpreadLogic_high or SSI_SpreadLogic_high
  4. route_design: Use AlternateCLBRouting
  5. RTL changes: Reduce fanout, pipeline long paths, reduce resource utilization

Predefined Implementation Strategies (Project Mode)

Performance-focused

Performance_Auto_1/2/3, Performance_Explore, Performance_ExplorePostRoutePhysOpt, Performance_ExploreWithRemap, Performance_WLBlockPlacement, Performance_WLBlockPlacementFanoutOpt, Performance_EarlyBlockPlacement, Performance_NetDelay_high/low, Performance_Retiming, Performance_ExtraTimingOpt, Performance_RefinePlacement, Performance_SpreadSLLs, Performance_BalanceSLLs, Performance_BalanceSLRs, Performance_HighUtilSLRs

Congestion-focused

Congestion_SpreadLogic_high/medium/low, Congestion_SSI_SpreadLogic_high/low

Area-focused

Area_Explore, Area_ExploreSequential, Area_ExploreWithRemap

© Shinei-Nouzen-Arch, GPL-2.0. Rendered from Markdown: HTML in the file is shown as text, images as links, and headings moved down two levels. Raw file

Files

SKILL.md and 8 other files in vivado-impl of Shinei-Nouzen-Arch/FPGA-Agent.

  • SKILL.md
  • REFERENCE.md
  • agents/openai.yaml
  • examples/ug906/TIMING-201/after/single_sdp_ram.sv
  • examples/ug906/TIMING-201/before/single_sdp_ram.sv
  • examples/ug906/TIMING-202/after/wide_mulitplier.sv
  • examples/ug906/TIMING-202/before/wide_mulitplier.sv
  • examples/ug906/UTIL-203/after/sp_rom.sv
  • examples/ug906/UTIL-203/before/sp_rom.v

Open the folder on GitHubat commit b60a52e

Compare with similar skills

Vivado Impl next to the 5 skills that share the most tags, products or categories with it. Stars are the repository's; “used in” counts other GitHub owners with a copy.

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Planning And Task Breakdownabashev/vfs-s31068 repos~1.9kAutomated safety check: PassApache-2.0
Incremental Implementationaddyosmani/agent-skills105k1 repos~2.3kAutomated safety check: PassMIT
ULW Plan Workflowcode-yeongyu/oh-my-openagent70k—~3.9kAutomated safety check: PassCustom licence
Ask NavigatorYeachan-Heo/oh-my-claudecode40k—~4.1kAutomated safety check: PassMIT

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Categories

Questions about Vivado Impl

What does Vivado Impl do?

A skill your agent uses when the user needs Vivado implementation strategy selection or optimization. Vivado Impl is an agent skill from Shinei-Nouzen-Arch/FPGA-Agent. Use this skill when the user needs Vivado implementation strategy selection or optimization.

When should I use Vivado Impl?

Vivado Impl fits situations like: the user needs Vivado implementation strategy selection; tasks that involve Task breakdown.

How do I install Vivado Impl in Claude Code?

Run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a claude-code`. Or copy the skill folder (vivado-impl in Shinei-Nouzen-Arch/FPGA-Agent) into .claude/skills/vivado-impl in your project. Claude Code loads it when a task matches its description.

How do I install Vivado Impl in Codex?

Run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a codex`. Or copy the skill folder (vivado-impl in Shinei-Nouzen-Arch/FPGA-Agent) into .agents/skills/vivado-impl in your project. Codex loads it when a task matches its description.

Can I use Vivado Impl in Cursor, Gemini CLI or GitHub Copilot?

Cursor, Gemini CLI, GitHub Copilot and OpenCode also load SKILL.md folders. With the skills CLI, run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-impl -a cursor` (or -a gemini-cli, github-copilot or opencode for the others). To copy it by hand, put the folder in .cursor/skills/vivado-impl, .gemini/skills/vivado-impl, .github/skills/vivado-impl and .opencode/skills/vivado-impl in your project.

What does Vivado Impl need to run?

SKILL.md names no scripts, command-line tools or credentials: Vivado Impl is instructions for the agent only.

Does Vivado Impl access the network?

SKILL.md contains no URLs. Any network use would come from the scripts or tools the agent runs. This is read from the text; nothing was executed.

Is Vivado Impl safe to install?

Our automated static check of SKILL.md found no risky patterns, such as piping downloads into a shell, reading credential files or hidden Unicode. It is not a guarantee. Review the folder before installing.

What licence does Vivado Impl use?

Vivado Impl is published under the GPL-2.0 licence (the repository's licence). It allows redistribution, so the full SKILL.md is shown on this page.

How many tokens does Vivado Impl use?

About 3.7k tokens (SKILL.md is roughly 15k characters). Agents keep only the skill's name and description in context until a task matches; then they load SKILL.md in full.

What are the alternatives to Vivado Impl?

Skills that share tags, products or a category with Vivado Impl: MemPalace Task Handoff (MemPalace/mempalace, 60k stars), Planning And Task Breakdown (abashev/vfs-s3, 106 stars), Incremental Implementation (addyosmani/agent-skills, 105k stars) and ULW Plan Workflow (code-yeongyu/oh-my-openagent, 70k stars). The comparison table on this page puts their stars, adoption, token cost, safety result and licence side by side.

Who maintains Vivado Impl?

Shinei-Nouzen-Arch (a GitHub user) maintains it in Shinei-Nouzen-Arch/FPGA-Agent, which has 180 GitHub stars. The repository holds 10 skills in this directory. The repository was last updated on September 5, 2026.

Source: Shinei-Nouzen-Arch/FPGA-Agent on GitHub. Facts on this page come from the repository at the commit we read; the author's words are quoted as theirs.