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Agent skill

Vivado Tcl

by Shinei-Nouzen-Arch in Shinei-Nouzen-Arch/FPGA-Agent

Generate, review, explain, and execute Vivado/Vitis TCL scripts for FPGA design flows, and verify their execution results.

GPL-2.0Auto-check passedDevelopment

Install Vivado Tcl

skills CLI
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-tcl -a claude-code

Project install by default; add -g for ~/.claude/skills/.

GitHub CLI
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-tcl --agent claude-code

Project scope by default; add --scope user for a personal install. Needs GitHub CLI 2.90.0 or later (public preview).

Manual copy
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .claude/skills && cp -r skills-src/vivado-tcl .claude/skills/vivado-tcl && rm -rf skills-src

Use ~/.claude/skills/ instead of .claude/skills for a personal install. The folder must contain SKILL.md.

Claude Code skills documentation · loads skills from .claude/skills/

Facts

Skill name
vivado-tcl
GitHub stars
180
Token cost
~2.5k tokens
SKILL.md length
707 words
Files
3
Skills in repo
10
Repo updated
First seen
Licence
GPL-2.0

At a glance

Generate, review, explain, and execute Vivado/Vitis TCL scripts for FPGA design flows, and verify their execution results.

  • Works in 6 steps: NEVER mix Project Mode and Non-Project… → Project Mode: uses create_project,… → Non-Project Mode: uses read_verilog,… → …
  • Explicit TCL requests
  • SKILL.md covers Overview, Critical Rules, Execution Model and Quick Reference: Project Mode…, plus 7 more sections
  • Instructions only: no scripts, shell commands, URLs or credentials in SKILL.md

What it does

Vivado Tcl is an agent skill from Shinei-Nouzen-Arch/FPGA-Agent. Generate, review, explain, and execute Vivado/Vitis TCL scripts for FPGA design flows, and verify their execution results. Covers project and non-project flows, synthesis, implementation, simulation, constraints, IP integration, and hardware programming. Use for explicit TCL requests or when scripting is needed to complete an already-authorized FPGA task; the user need not name TCL again. For pure report interpretation, strategy selection, constraint theory, or debug planning, use the relevant analysis…

Its SKILL.md is about 2.5k tokens, which your agent loads only when the skill is triggered. The skill folder holds 3 other files (for example `REFERENCE.md` and `agents/openai.yaml`).

It sits in Development. The licence is GPL-2.0.

When your agent uses it

  • Explicit TCL requests
  • Scripting is needed to complete an already-authorized FPGA task
  • The user need not name TCL again

Example prompts

  • “/vivado-tcl”

Workflow steps

6 steps, taken from the first numbered list in SKILL.md.

  1. NEVER mix Project Mode and Non-Project Mode commands — they are incompatible flows
  2. Project Mode: uses create_project, add_files, launch_runs, wait_on_run, open_run
  3. Non-Project Mode: uses read_verilog, synth_design, opt_design, place_design, route_design
  4. Determine the mode from existing evidence first: inspect the project, scripts, configuration, and prior user instructions. Preserve an…
  5. Verify execution as part of this skill: inspect exit status, run status, relevant logs/reports, and requested artifacts. Use…
  6. Match the requested action: review or script generation ends with the requested analysis or checked script, not an automatic execution. An…

What it can do on your machine

Read from SKILL.md and the folder at commit b60a52e. It shows what the files ask for, not the result of running them.

  • Tool permissions

    Pre-approves nothing: there is no allowed-tools line, so your agent's usual permission prompts apply.

    From allowed-tools in the SKILL.md frontmatter.

  • Runs code

    No scripts in the folder and no shell commands in SKILL.md (its code samples are tcl and bash).

    From the folder's file list and the shell code blocks in SKILL.md.

  • Network

    No URLs in SKILL.md.

    From URLs in SKILL.md, links to its own repository left out.

  • Credentials

    Names no API keys, tokens, secrets or passwords.

    From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.

Context cost

Vivado Tcl loads about 2.5k tokens when it runs. Until then it costs about 169 tokens; SKILL.md has 707 words of instructions outside code blocks.

Always · name and description, kept in context so the agent knows when to use it
~169
When it runs · the whole SKILL.md, loaded when a task matches
~2.5k

Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.

Safety

Auto-check passed

The automated check found no risky patterns in SKILL.md.

Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.

SKILL.md

The full file from Shinei-Nouzen-Arch/FPGA-Agent at commit b60a52e, republished under its GPL-2.0 licence (© Shinei-Nouzen-Arch). 707 words, ~2,511 tokens.

Download SKILL.mdSave it as .claude/skills/vivado-tcl/SKILL.md (or your agent's skills folder). This skill also uses 2 other files; get the full folder from GitHub.
name
vivado-tcl
description
Generate, review, explain, and execute Vivado/Vitis TCL scripts for FPGA design flows, and verify their execution results. Covers project and non-project flows, synthesis, implementation, simulation, constraints, IP integration, and hardware programming. Use for explicit TCL requests or when scripting is needed to complete an already-authorized FPGA task; the user need not name TCL again. For pure report interpretation, strategy selection, constraint theory, or debug planning, use the relevant analysis, synthesis, implementation, constraints, or debug skill as the primary guide. Combine those skills with this one when execution and verification are needed.

Vivado TCL Script Generation Guide

Overview

This skill generates and reviews Vivado TCL scripts and, when execution is part of the user's request, runs them via vivado -mode batch and verifies the results. It covers project creation, synthesis, implementation, bitstream generation, hardware programming, IP integration, debug, and simulation. For the complete command reference, see REFERENCE.md.

Critical Rules

  1. NEVER mix Project Mode and Non-Project Mode commands — they are incompatible flows
  2. Project Mode: uses create_project, add_files, launch_runs, wait_on_run, open_run
  3. Non-Project Mode: uses read_verilog, synth_design, opt_design, place_design, route_design
  4. Determine the mode from existing evidence first: inspect the project, scripts, configuration, and prior user instructions. Preserve an established flow. For a new flow, choose a suitable mode and state the assumption unless the choice materially changes the requested deliverable or execution scope. Ask only for consequential information that cannot be established from available evidence; do not re-ask answered questions or invent a target device needed for execution.
  5. Verify execution as part of this skill: inspect exit status, run status, relevant logs/reports, and requested artifacts. Use vivado-analysis or other relevant skills for deeper design decisions while continuing the same task; switching skills does not require the user to repeat authorization.
  6. Match the requested action: review or script generation ends with the requested analysis or checked script, not an automatic execution. An execution or fix request includes its necessary in-scope validation and follow-up. Existing authorization remains valid; skill selection does not authorize additional design changes, hardware programming, or hardware writes.

Execution Model

How to run a TCL script
bash
# Batch mode (recommended for automation)
vivado -mode batch -source <script.tcl>

# With arguments
vivado -mode batch -source script.tcl -tclargs "ARG1=value1"

# Interactive TCL shell
vivado -mode tcl
Key output files
  • vivado.log — full session log
  • vivado.jou — journal of TCL commands (reusable as script)
  • *.dcp — design checkpoints (snapshots of design state)
  • *.bit — bitstream files
  • *.xsa — hardware platform for Vitis
  • *.ltx — debug probes file

Quick Reference: Project Mode Flow

tcl
# 1. Create project
create_project <name> <dir> -part <part>

# 2. Add sources
add_files {./src/top.v ./src/sub.v}
add_files -fileset constrs_1 ./constraints/timing.xdc
update_compile_order -fileset sources_1

# 3. Synthesis
launch_runs synth_1
wait_on_run synth_1

# 4. Open synth results & reports
open_run synth_1 -name netlist_1
report_timing_summary -file syn_timing.rpt
report_power -file syn_power.rpt

# 5. Implementation through routing
launch_runs impl_1 -to_step route_design
wait_on_run impl_1

# 6. Reports
open_run impl_1
report_timing_summary -delay_type min_max -file imp_timing.rpt
report_route_status -file imp_route_status.rpt
check_timing -file imp_check_timing.rpt
report_drc -file imp_drc.rpt
report_utilization -file imp_util.rpt
report_power -file imp_power.rpt

Inspect the run status and reports against the task's acceptance criteria before the output stage. When bitstream generation is in scope and those checks pass, continue without another confirmation:

tcl
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1

Quick Reference: Non-Project Mode Flow

tcl
# 0. Setup
set outputDir ./output
file mkdir $outputDir

# 1. Read sources
read_verilog {./src/top.v ./src/sub.v}
read_xdc ./constraints/timing.xdc

# 2. Synthesis
synth_design -top <top_module> -part <part>
write_checkpoint -force $outputDir/post_synth.dcp
report_timing_summary -file $outputDir/post_synth_timing.rpt

# 3. Implementation
opt_design
place_design
# Optional: phys_opt_design
route_design
write_checkpoint -force $outputDir/post_route.dcp

# 4. Reports
report_timing_summary -file $outputDir/post_route_timing.rpt
report_route_status -file $outputDir/post_route_status.rpt
check_timing -file $outputDir/post_route_check_timing.rpt
report_utilization -file $outputDir/post_route_util.rpt
report_power -file $outputDir/post_route_power.rpt
report_drc -file $outputDir/post_route_drc.rpt

After the applicable acceptance checks pass, generate a bitstream if requested. For unattended automation, encode the checks as failure conditions before this output block; merely producing reports is not verification.

tcl
# 5. Generate the requested bitstream in the selected task output location
write_bitstream -force $outputDir/top.bit

IP Integrator (Block Design)

tcl
# Create block design
create_bd_design "system"

# Add IP cores
create_bd_cell -type ip -vlnv xilinx.com:ip:<ip_name>:<version> <instance>

# Run automation (AXI connections, external ports)
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 \
    -config {make_external "FIXED_IO, DDR"} [get_bd_cells ps7_0]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 \
    -config {Master "/ps7_0/M_AXI_GP0"} [get_bd_intf_pins peripheral/S_AXI]

# Validate, save, generate wrapper
assign_bd_address
validate_bd_design
save_bd_design
make_wrapper -files [get_files system.bd] -top

When a Vitis platform export is requested, first build the design and verify its applicable acceptance criteria and required bitstream using the relevant flow above. Then export to the selected output path:

tcl
write_hw_platform -fixed -include_bit -force ./system_wrapper.xsa

Hardware Programming

tcl
open_hw_manager
connect_hw_server -url localhost:3121
open_hw_target

current_hw_device [get_hw_devices <device>]
set_property PROGRAM.FILE {<bitstream>.bit} [current_hw_device]
set_property PROBES.FILE {<probes>.ltx} [current_hw_device]
program_hw_devices [current_hw_device]

close_hw_target
disconnect_hw_server
close_hw_manager

Debug Core Insertion (ILA)

tcl
# After synthesis, before implementation
open_run synth_1

# Create ILA
create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]

# Connect clock
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets clk]

# Add probes
set_property port_width <width> [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets {<signal_list>}]

# Implement and write probes
implement_debug_core
write_debug_probes -force ./output/top.ltx

TCL Syntax Tips

Object queries
tcl
get_cells -hierarchical -filter "lib_cell =~ FD*"
get_pins -of [get_cells inst_1]
get_nets -of [get_pins inst_1/D]
get_property loc [get_cells inst_1]
set_property loc SLICE_X1Y27 [get_cells inst_1]
Bus indexing
tcl
add_wave {bus[4]}       ;# braces for square brackets
add_wave bus(4)         ;# parentheses work too
Show full SKILL.md (297 more words)Show less
Error handling
tcl
if {[catch {<command>} result options]} {
    puts stderr "Error: $result"
    return -options $options $result
}

Propagate an unhandled stage failure to the batch caller; logging an error alone must not allow dependent stages to appear successful. When a fix is in scope, inspect the failure and make a relevant correction before retrying.

Workflow Guidelines

  1. For batch execution, write TCL to a .tcl file first, then run it with vivado -mode batch -source. For generation or review only, deliver the checked script or findings without executing the flow.
  2. Include file mkdir for output directories to avoid errors
  3. Use write_checkpoint at key stages in Non-Project Mode for recovery
  4. Verify the stages actually run: check run status and relevant logs, reports, and artifacts. Include report_timing_summary after synthesis and routing when those stages are in scope. Apply the full timing acceptance criteria before claiming timing closure; otherwise report the validation appropriate to the requested stage.
  5. Limit -force to replaceable task outputs or already-authorized overwrites. Establish ownership and replaceability from the task context, file provenance, and output paths; this is an evidence check, not a per-run user confirmation. Use a fresh output path for other existing files. Ask only when an overwrite is necessary and not already authorized. All -force examples here and in REFERENCE.md assume this output ownership check has been made.
  6. For IP Integrator flows, always validate_bd_design before proceeding
  7. When programming hardware, always check device connection before programming
  8. Complete the requested outcome: a script launch, successful process exit, or generated report alone is not proof of success. Continue necessary authorized work; if a required step cannot be completed, identify the specific missing result and finish unaffected work without claiming the whole task is complete.

Common Part Numbers (examples)

FamilyPart Example
Kintex-7xc7k70tfbg484-2
Zynq-7000xc7z020clg484-1
Artix-7xc7a35tcpg236-1
Kintex UltraScale+xcku5p-ffvb676-2-e
Zynq UltraScale+xczu9eg-ffvb1156-2-e
Versalxcvm1802-vsva2197-2MP-e-S

© Shinei-Nouzen-Arch, GPL-2.0. Rendered from Markdown: HTML in the file is shown as text, images as links, and headings moved down two levels. Raw file

Files

SKILL.md and 2 other files in vivado-tcl of Shinei-Nouzen-Arch/FPGA-Agent.

  • SKILL.md
  • REFERENCE.md
  • agents/openai.yaml

Open the folder on GitHubat commit b60a52e

Compare with similar skills

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Vivado Tcl compared with similar skills
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Vivado Tcl this skillShinei-Nouzen-Arch/FPGA-Agent180—~2.5kAutomated safety check: PassGPL-2.0
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Finishing a Development Branchobra/superpowers297k5 repos~1.9kAutomated safety check: PassMIT
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PR Babysitteropeninterpreter/openinterpreter69k3 repos~4.2kAutomated safety check: PassApache-2.0
Code Review ChecklistshareAI-lab/learn-claude-code78k4 repos~1.1kAutomated safety check: PassMIT

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  • Vivado Debug

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  • Vivado Analysis

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    A skill your agent uses when the user needs Vivado design analysis, timing report interpretation, or timing-closure diagnosis.

    180 GitHub stars~3.3k tokensUpdated 1 mo ago
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  • Vivado Constraints

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    A skill your agent uses when the user needs help writing XDC/SDC timing or physical constraints for Vivado FPGA designs.

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  • Vivado Impl

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    A skill your agent uses when the user needs Vivado implementation strategy selection or optimization.

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  • Vivado Sim

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  • Vivado Synth

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Categories

Questions about Vivado Tcl

What does Vivado Tcl do?

Generate, review, explain, and execute Vivado/Vitis TCL scripts for FPGA design flows, and verify their execution results. Vivado Tcl is an agent skill from Shinei-Nouzen-Arch/FPGA-Agent. Generate, review, explain, and execute Vivado/Vitis TCL scripts for FPGA design flows, and verify their execution results.

When should I use Vivado Tcl?

Vivado Tcl fits situations like: explicit TCL requests; scripting is needed to complete an already-authorized FPGA task; the user need not name TCL again.

How do I install Vivado Tcl in Claude Code?

Run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-tcl -a claude-code`. Or copy the skill folder (vivado-tcl in Shinei-Nouzen-Arch/FPGA-Agent) into .claude/skills/vivado-tcl in your project. Claude Code loads it when a task matches its description.

How do I install Vivado Tcl in Codex?

Run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-tcl -a codex`. Or copy the skill folder (vivado-tcl in Shinei-Nouzen-Arch/FPGA-Agent) into .agents/skills/vivado-tcl in your project. Codex loads it when a task matches its description.

Can I use Vivado Tcl in Cursor, Gemini CLI or GitHub Copilot?

Cursor, Gemini CLI, GitHub Copilot and OpenCode also load SKILL.md folders. With the skills CLI, run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-tcl -a cursor` (or -a gemini-cli, github-copilot or opencode for the others). To copy it by hand, put the folder in .cursor/skills/vivado-tcl, .gemini/skills/vivado-tcl, .github/skills/vivado-tcl and .opencode/skills/vivado-tcl in your project.

What does Vivado Tcl need to run?

SKILL.md names no scripts, command-line tools or credentials: Vivado Tcl is instructions for the agent only.

Does Vivado Tcl access the network?

SKILL.md contains no URLs. Any network use would come from the scripts or tools the agent runs. This is read from the text; nothing was executed.

Is Vivado Tcl safe to install?

Our automated static check of SKILL.md found no risky patterns, such as piping downloads into a shell, reading credential files or hidden Unicode. It is not a guarantee. Review the folder before installing.

What licence does Vivado Tcl use?

Vivado Tcl is published under the GPL-2.0 licence (the repository's licence). It allows redistribution, so the full SKILL.md is shown on this page.

How many tokens does Vivado Tcl use?

About 2.5k tokens (SKILL.md is roughly 10k characters). Agents keep only the skill's name and description in context until a task matches; then they load SKILL.md in full.

What are the alternatives to Vivado Tcl?

Skills that share tags, products or a category with Vivado Tcl: Vercel Composition Patterns (supabase/supabase, 111k stars), Finishing a Development Branch (obra/superpowers, 297k stars), Typescript Advanced Types (rolling-scopes/rsschool-app, 10k stars) and PR Babysitter (openinterpreter/openinterpreter, 69k stars). The comparison table on this page puts their stars, adoption, token cost, safety result and licence side by side.

Who maintains Vivado Tcl?

Shinei-Nouzen-Arch (a GitHub user) maintains it in Shinei-Nouzen-Arch/FPGA-Agent, which has 180 GitHub stars. The repository holds 10 skills in this directory. The repository was last updated on September 5, 2026.

Source: Shinei-Nouzen-Arch/FPGA-Agent on GitHub. Facts on this page come from the repository at the commit we read; the author's words are quoted as theirs.