Vivado Constraints

# Project Mode: set on XDC file objects
set_property USED_IN_SYNTHESIS TRUE [get_files timing.xdc]
set_property USED_IN_IMPLEMENTATION TRUE [get_files timing.xdc]
set_property USED_IN_SYNTHESIS FALSE [get_files physical.xdc]  ;# impl only

# Non-Project Mode: just read in appropriate order
read_xdc timing.xdc        ;# both synth and impl
read_xdc physical.xdc      ;# read after synth only

# Project Mode
set_property SCOPED_TO_REF uart_tx_ctl [get_files uart_tx_ctl.xdc]
set_property SCOPED_TO_CELLS uart_tx_i0/uart_tx_ctl_i0 [get_files uart_tx_ctl.xdc]

# Non-Project Mode
read_xdc -ref uart_tx_ctl uart_tx_ctl.xdc
read_xdc -cells uart_tx_i0/uart_tx_ctl_i0 uart_tx_ctl.xdc

# Board clock on input port (RECOMMENDED)
create_clock -period 10 [get_ports sysclk]

# Named clock with custom waveform (25% duty cycle, 90° phase shift)
create_clock -name devclk -period 10 -waveform {2.5 5} [get_ports ClkIn]

# Differential clock — define on POSITIVE pin ONLY
create_clock -name sysclk -period 3.33 [get_ports SYS_CLK_clk_p]

# GT recovered clock
create_clock -name rxclk -period 3.33 [get_pins gt0/RXOUTCLK]

# Virtual clock (no netlist object — for I/O delay reference)
create_clock -name clk_virt -period 10

# MMCM/PLL outputs → AUTO-DERIVED, no manual constraint needed
# User logic divider → must define manually:
create_generated_clock -name clkdiv2 -source [get_ports clkin] -divide_by 2 [get_pins REGA/Q]

# Using -edges (edge indices of master clock)
create_generated_clock -name clkdiv2 -source [get_pins REGA/C] -edges {1 3 5} [get_pins REGA/Q]

# Duty cycle change + phase shift via -edges and -edge_shift
create_generated_clock -name clkshift -source [get_pins mmcm0/CLKIN] \
    -edges {1 2 3} -edge_shift {2.5 0 2.5} [get_pins mmcm0/CLKOUT]

# Multiply + divide (for MMCM manual definition)
create_generated_clock -name clk43 -source [get_pins mmcm0/CLKIN] \
    -multiply_by 4 -divide_by 3 [get_pins mmcm0/CLKOUT]

# Combinational path only (MUX output)
create_generated_clock -name clkout -source [get_pins mmcm0/CLKIN] \
    -combinational [get_pins MUX/O]

# Rename auto-derived clock (name + source_object only)
create_generated_clock -name clk_rx [get_pins clk_gen_i0/clk_core_i0/inst/mmcm_adv_inst/CLKOUT0]

# Asynchronous clocks (most common — separate oscillators)
set_clock_groups -name async_clk0_clk1 -asynchronous \
    -group {clk0 usrclk itfclk} -group {clk1 gtclkrx gtclktx}

# With -include_generated_clocks (auto-include derived clocks)
set_clock_groups -name async_grp -asynchronous \
    -group [get_clocks -include_generated_clocks clk0] \
    -group [get_clocks -include_generated_clocks clk1]

# Exclusive clocks (BUFGMUX — only one active at a time)
set_clock_groups -name exclusive_clk0_clk1 -physically_exclusive \
    -group clk0 -group clk1

# Source latency (board-level delay, outside FPGA)
set_clock_latency -source -early 0.2 [get_clocks sysClk]
set_clock_latency -source -late 0.5 [get_clocks sysClk]

# Input jitter (primary clocks only, per-clock)
set_input_jitter [get_clocks -of_objects [get_ports clkin]] 0.1

# System jitter (global, all clocks)
set_system_jitter 0.05

# Additional clock uncertainty (extra timing margin)
set_clock_uncertainty 0.5 [get_clocks clk1]

# Inter-clock uncertainty (MUST define BOTH directions)
set_clock_uncertainty 2.0 -from [get_clocks clk1] -to [get_clocks clk2]
set_clock_uncertainty 2.0 -from [get_clocks clk2] -to [get_clocks clk1]

# Basic (both min and max)
set_input_delay -clock sysClk 2 [get_ports DIN]

# Separate min/max
set_input_delay -clock sysClk -max 4 [get_ports DIN]
set_input_delay -clock sysClk -min 1 [get_ports DIN]

# Relative to virtual clock
create_clock -name clk_port_virt -period 10
set_input_delay -clock clk_port_virt 2 [get_ports DIN]

create_clock -name clk_ddr -period 6 [get_ports DDR_CLK_IN]
set_input_delay -clock clk_ddr -max 2.1 [get_ports DDR_IN]
set_input_delay -clock clk_ddr -max 1.9 [get_ports DDR_IN] -clock_fall -add_delay
set_input_delay -clock clk_ddr -min 0.9 [get_ports DDR_IN]
set_input_delay -clock clk_ddr -min 1.1 [get_ports DDR_IN] -clock_fall -add_delay

set_output_delay -clock sysClk 6 [get_ports DOUT]

# Separate min/max
set_output_delay -clock sysClk -max 6 [get_ports DOUT]
set_output_delay -clock sysClk -min 1 [get_ports DOUT]

create_clock -name clk_ddr -period 6 [get_ports DDR_CLK_IN]
set_output_delay -clock clk_ddr -max 2.1 [get_ports DDR_OUT]
set_output_delay -clock clk_ddr -max 1.9 [get_ports DDR_OUT] -clock_fall -add_delay
set_output_delay -clock clk_ddr -min 0.9 [get_ports DDR_OUT]
set_output_delay -clock clk_ddr -min 1.1 [get_ports DDR_OUT] -clock_fall -add_delay

create_clock -name sysClk -period 10
set_input_delay -clock sysClk 4 [get_ports DIN]
set_output_delay -clock sysClk 1 [get_ports DOUT]
# Effective budget: 10 - 4 - 1 = 5 ns