Vivado Sim

What it does

When your agent uses it

• The user needs help with Vivado simulation strategy
• Tasks that involve Experimental design
• Tasks that involve Debugging

Example prompts

• “/vivado-sim”

Requirements

• A Bash shell

Workflow steps

3 steps, taken from the step headings in SKILL.md.

1. 1Compile Simulation Libraries (One-Time)
2. 2Set Target Simulator
3. 3Export Simulation Scripts

What it can do on your machine

Read from SKILL.md and the folder at commit b60a52e. It shows what the files ask for, not the result of running them.

• Tool permissions

  Pre-approves nothing: there is no allowed-tools line, so your agent's usual permission prompts apply.

  From allowed-tools in the SKILL.md frontmatter.

• Runs code

  Ships script files (Shell), which the agent can run.

  From the folder's file list and the shell code blocks in SKILL.md.

• Network

  No URLs in SKILL.md.

  From URLs in SKILL.md, links to its own repository left out.

• Credentials

  Names no API keys, tokens, secrets or passwords.

  From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.

Context cost

Vivado Sim loads about 2.9k tokens when it runs. Until then it costs about 243 tokens; SKILL.md has 577 words of instructions outside code blocks.

Always · name and description, kept in context so the agent knows when to use it

~243

When it runs · the whole SKILL.md, loaded when a task matches

~2.9k

Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.

Safety

Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.

SKILL.md

The full file from Shinei-Nouzen-Arch/FPGA-Agent at commit b60a52e, republished under its GPL-2.0 licence (© Shinei-Nouzen-Arch). 577 words, ~2,941 tokens.

name

vivado-sim

description

Use this skill when the user needs help with Vivado simulation strategy, flow selection, and debugging. This includes behavioral simulation (RTL functional verification), post-synthesis simulation (netlist functional verification), post-implementation timing simulation (SDF back-annotation, timing verification), Vivado Simulator xsim usage (xvlog/xvhdl/xelab/xsim three-step flow, launch_simulation Project Mode), third-party simulator integration (Questa/ModelSim/VCS/Xcelium/Riviera/ActiveHDL, compile_simlib, export_simulation), SAIF/VCD power simulation (open_saif/log_saif, open_vcd/log_vcd, read_saif + report_power), simulation netlist generation (write_verilog -mode funcsim/timesim, write_sdf), xsim debugging commands (add_force, add_wave, log_wave, add_bp, step, run, restart, get_objects, get_value), simulation properties and settings, glbl.v usage, or any question about choosing the right simulation approach for verification or power analysis.

RTL + Testbench ──→ Behavioral Sim (functional verification, fastest)
       ↓ synth_design
Synthesized Netlist ──→ Post-Synth Sim (synthesis correctness, optional)
       ↓ place_design + route_design
Implemented Netlist + SDF ──→ Timing Sim (timing verification, slowest)
       ↓
SAIF/VCD ──→ report_power (power analysis)

# Configure simulation settings
set_property -name {xsim.simulate.runtime} -value {1000ns} -objects [get_filesets sim_1]
set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]
set_property -name {xsim.elaborate.debug_level} -value {typical} -objects [get_filesets sim_1]

# Launch behavioral simulation
launch_simulation
run 100ns
close_sim

launch_simulation -mode behavioral          ;# RTL sim (default)
launch_simulation -mode post-synthesis -type functional   ;# Post-synth functional
launch_simulation -mode post-synthesis -type timing       ;# Post-synth timing
launch_simulation -mode post-implementation -type functional  ;# Post-impl functional
launch_simulation -mode post-implementation -type timing      ;# Post-impl timing

launch_simulation -scripts_only             ;# Generate sim scripts only
launch_simulation -scripts_only -absolute_path  ;# With absolute paths

# Step 1: Compile
exec xvlog design.v tb.v                    ;# Verilog
exec xvlog -sv design.sv                    ;# SystemVerilog
exec xvhdl design.vhd                       ;# VHDL
exec xvhdl -2008 design.vhd                 ;# VHDL-2008

# Step 2: Elaborate (link)
exec xelab -debug typical tb_top -s sim_snap

# Step 3: Simulate
exec xsim sim_snap -runall
exec xsim sim_snap -t run.tcl               ;# With TCL script
exec xsim sim_snap -gui                     ;# With GUI

# Constant force
add_force clk 0
# Clock pattern: 0 at 0ns, 1 at 5ns, repeat every 10ns
add_force clk {0} {1 5ns} -repeat_every 10ns
# Reset pulse: 1 at 0ns, 0 at 100ns
add_force rst {1} {0 100ns}
# With radix
add_force -radix hex data_in 0xFF

# Post-synthesis functional netlist
open_checkpoint post_synth.dcp
write_verilog -mode funcsim -force post_synth_func.v

# Post-implementation timing netlist + SDF
open_checkpoint post_route.dcp
write_verilog -mode timesim -sdf_anno true -force post_impl_timing.v
write_sdf -force post_impl_timing.sdf

# VHDL variants
write_vhdl -mode funcsim -force post_synth_func.vhd

# xelab with timing simulation netlist
exec xelab -debug typical tb_top glbl \
    -transport_int_delays \
    -pulse_r 0 -pulse_e 0 \
    -s timing_sim_snap

exec xelab -debug typical tb_top glbl \
    -sdfroot /tb_top/uut \
    -transport_int_delays \
    -pulse_r 0 -pulse_e 0 \
    -s timing_sim_snap

write_sdf -process_corner fast -force fast_corner.sdf   ;# Best case
write_sdf -process_corner slow -force slow_corner.sdf   ;# Worst case (default)

# Include glbl.v in compilation and elaboration
exec xvlog $::env(XILINX_VIVADO)/data/verilog/src/glbl.v
exec xelab tb_top glbl -debug typical -s sim_snap

compile_simlib -simulator questa -directory /path/to/compiled_libs \
    -family all -language all

set_property target_simulator Questa [current_project]
# Or: ModelSim, VCS, Xcelium, Riviera, ActiveHDL

# Option A: export_simulation (flexible, supports Non-Project)
export_simulation -simulator questa -directory ./sim_scripts \
    -use_ip_compiled_libs

# Option B: launch_simulation -scripts_only (Project Mode only)
launch_simulation -scripts_only

# During simulation (xsim)
open_saif /path/to/output.saif
log_saif [get_objects -r *]       ;# Or specific hierarchy
run 1000ns
close_saif

# Power analysis
open_checkpoint post_route.dcp
read_saif /path/to/output.saif
report_power -file power.rpt

open_vcd /path/to/output.vcd
log_vcd [get_objects -r *]
run 1000ns
close_vcd

# Runtime
set_property -name {xsim.simulate.runtime} -value {1000ns} -objects [get_filesets sim_1]

# Log all signals
set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]

# Debug level: typical | all | off
set_property -name {xsim.elaborate.debug_level} -value {typical} -objects [get_filesets sim_1]

# Additional xsim options
set_property -name {xsim.simulate.xsim.more_options} -value {-testplusarg FAST} -objects [get_filesets sim_1]

# Additional xelab options
set_property -name {xsim.elaborate.xelab.more_options} -value {-mt 4} -objects [get_filesets sim_1]

# Waveform database file
set_property -name {xsim.simulate.wdb} -value {my_sim.wdb} -objects [get_filesets sim_1]

# Target simulator
set_property target_simulator Questa [current_project]

# Add simulation source
add_files -fileset sim_1 tb_top.v

# Set top module
set_property top tb_top [get_filesets sim_1]

# Set top library
set_property top_lib work [get_filesets sim_1]

# Create additional sim fileset
create_fileset -simset sim_2

© Shinei-Nouzen-Arch, GPL-2.0. Rendered from Markdown: HTML in the file is shown as text, images as links, and headings moved down two levels. Raw file

Files

SKILL.md and 4 other files in vivado-sim of Shinei-Nouzen-Arch/FPGA-Agent.

• SKILL.md
• REFERENCE.md
• agents/openai.yaml
• evals/run_eval.sh
• evals/trigger_eval.json

Open the folder on GitHubat commit b60a52e