Vercel Composition Patterns
supabase/supabase
React composition patterns that scale. An agent skill from supabase/supabase.
A skill your agent uses when the user needs Vivado design analysis, timing report interpretation, or timing-closure diagnosis.
Install Vivado Analysis
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-analysis -a claude-codeProject install by default; add -g for ~/.claude/skills/.
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-analysis --agent claude-codeProject scope by default; add --scope user for a personal install. Needs GitHub CLI 2.90.0 or later (public preview).
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .claude/skills && cp -r skills-src/vivado-analysis .claude/skills/vivado-analysis && rm -rf skills-srcUse ~/.claude/skills/ instead of .claude/skills for a personal install. The folder must contain SKILL.md.
Claude Code skills documentation · loads skills from .claude/skills/
Install the "vivado-analysis" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-analysis into .claude/skills/vivado-analysis/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-analysis", then confirm the skill loads.Claude Code copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.
$skill-installer install https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-analysisType this inside Codex. $skill-installer <name> installs a curated skill from openai/skills. The installer writes to $CODEX_HOME/skills (default ~/.codex/skills). Restart Codex if the skill does not show up.
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-analysis -a codexProject install goes to .agents/skills/; add -g for ~/.codex/skills/.
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-analysis --agent codexProject scope by default (.agents/skills/); add --scope user for a personal install.
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .agents/skills && cp -r skills-src/vivado-analysis .agents/skills/vivado-analysis && rm -rf skills-srcUse ~/.agents/skills/ instead of .agents/skills for a personal install.
Codex skills documentation · loads skills from .agents/skills/
Install the "vivado-analysis" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-analysis into .agents/skills/vivado-analysis/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-analysis", then confirm the skill loads.Codex copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-analysis -a cursorProject install goes to .agents/skills/; add -g for ~/.cursor/skills/.
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-analysis --agent cursorProject scope by default (.agents/skills/); add --scope user for a personal install.
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .cursor/skills && cp -r skills-src/vivado-analysis .cursor/skills/vivado-analysis && rm -rf skills-srcUse ~/.cursor/skills/ instead of .cursor/skills for a personal install.
Cursor skills documentation · loads skills from .cursor/skills/, .agents/skills/, .claude/skills/, .codex/skills/
Install the "vivado-analysis" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-analysis into .cursor/skills/vivado-analysis/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-analysis", then confirm the skill loads.Cursor copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.
$ gemini skills install https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git --path vivado-analysis--scope user (default) or --scope workspace; --path is the subfolder of the repo that holds the skill; --consent skips the security confirmation prompt.
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-analysis -a gemini-cliProject install goes to .agents/skills/; add -g for ~/.gemini/skills/.
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-analysis --agent gemini-cliProject scope by default (.agents/skills/); add --scope user for a personal install.
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .gemini/skills && cp -r skills-src/vivado-analysis .gemini/skills/vivado-analysis && rm -rf skills-srcUse ~/.gemini/skills/ instead of .gemini/skills for a personal install, then run /skills reload.
Gemini CLI skills documentation · loads skills from .gemini/skills/, .agents/skills/
Install the "vivado-analysis" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-analysis into .gemini/skills/vivado-analysis/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-analysis", then confirm the skill loads.Gemini CLI copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-analysisInstalls for Copilot at project scope by default; add --scope user for a personal install. Preview a skill first with gh skill preview. Needs GitHub CLI 2.90.0 or later (public preview).
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-analysis -a github-copilotProject install goes to .agents/skills/; add -g for ~/.copilot/skills/.
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .github/skills && cp -r skills-src/vivado-analysis .github/skills/vivado-analysis && rm -rf skills-srcUse ~/.copilot/skills/ instead of .github/skills for a personal install. Commit .github/skills so cloud agent and code review can use it.
GitHub Copilot skills documentation · loads skills from .github/skills/, .claude/skills/, .agents/skills/
Install the "vivado-analysis" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-analysis into .github/skills/vivado-analysis/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-analysis", then confirm the skill loads.GitHub Copilot copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.
$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-analysis -a opencodeOpenCode documents no install command of its own. Project install goes to .agents/skills/; add -g for ~/.config/opencode/skills/.
$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-analysis --agent opencodeProject scope by default (.agents/skills/); add --scope user for a personal install.
$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .opencode/skills && cp -r skills-src/vivado-analysis .opencode/skills/vivado-analysis && rm -rf skills-srcUse ~/.config/opencode/skills/ instead of .opencode/skills for a personal install.
OpenCode skills documentation · loads skills from .opencode/skills/, .claude/skills/, .agents/skills/
Install the "vivado-analysis" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-analysis into .opencode/skills/vivado-analysis/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-analysis", then confirm the skill loads.OpenCode copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.
Facts
- Skill name
vivado-analysis- GitHub stars
- 180
- Token cost
- ~3.3k tokens
- SKILL.md length
- 1,117 words
- Files
- 3
- Skills in repo
- 10
- Repo updated
- First seen
- Licence
- GPL-2.0
At a glance
A skill your agent uses when the user needs Vivado design analysis, timing report interpretation, or timing-closure diagnosis.
- The user needs Vivado design analysis
- SKILL.md covers Timing Path Fundamentals, Max/Min Delay Analysis Corner…, Report Selection Guide and Timing Report Header Fields, plus 8 more sections
- Instructions only: no scripts, shell commands, URLs or credentials in SKILL.md
- Timing report interpretation
What it does
Vivado Analysis is an agent skill from Shinei-Nouzen-Arch/FPGA-Agent. Use this skill when the user needs Vivado design analysis, timing report interpretation, or timing-closure diagnosis. Covers reporttiming/reporttimingsummary, slack and path analysis, clock skew/uncertainty, reportqorassessment/suggestions, reportdesignanalysis for congestion and complexity, reportmethodology, utilization, CDC/DRC/bus skew reports, message severity, waivers, and setup/hold closure strategy. This skill interprets reports and recommends next analysis steps. For TCL execution use vivado-tcl, for…
Its SKILL.md is about 3.3k tokens, which your agent loads only when the skill is triggered. The skill folder holds 3 other files (for example `REFERENCE.md` and `agents/openai.yaml`).
It sits in Development. The licence is GPL-2.0.
When your agent uses it
- The user needs Vivado design analysis
- Timing report interpretation
- Timing-closure diagnosis
Example prompts
- “/vivado-analysis”
What it can do on your machine
Read from SKILL.md and the folder at commit b60a52e. It shows what the files ask for, not the result of running them.
Tool permissions
Pre-approves nothing: there is no allowed-tools line, so your agent's usual permission prompts apply.
From allowed-tools in the SKILL.md frontmatter.
Runs code
No scripts in the folder and no shell commands in SKILL.md (its code samples are verilog).
From the folder's file list and the shell code blocks in SKILL.md.
Network
No URLs in SKILL.md.
From URLs in SKILL.md, links to its own repository left out.
Credentials
Names no API keys, tokens, secrets or passwords.
From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.
Context cost
Vivado Analysis loads about 3.3k tokens when it runs. Until then it costs about 172 tokens; SKILL.md has 1,117 words of instructions outside code blocks.
Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.
Safety
Auto-check passed
The automated check found no risky patterns in SKILL.md.
Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.
SKILL.md
The full file from Shinei-Nouzen-Arch/FPGA-Agent at commit b60a52e, republished under its GPL-2.0 licence (© Shinei-Nouzen-Arch). 1,117 words, ~3,319 tokens.
Download SKILL.mdSave it as
.claude/skills/vivado-analysis/SKILL.md (or your agent's skills folder). This skill also uses 2 other files; get the full folder from GitHub.- name
- vivado-analysis
- description
- Use this skill when the user needs Vivado design analysis, timing report interpretation, or timing-closure diagnosis. Covers report_timing/report_timing_summary, slack and path analysis, clock skew/uncertainty, report_qor_assessment/suggestions, report_design_analysis for congestion and complexity, report_methodology, utilization, CDC/DRC/bus skew reports, message severity, waivers, and setup/hold closure strategy. This skill interprets reports and recommends next analysis steps. For TCL execution use vivado-tcl, for constraint changes use vivado-constraints, for implementation directives use vivado-impl, for full timing closure workflows use vivado-timing-closure.
Vivado Design Analysis & Timing Closure Guide
Based on UG906 (v2025.2). This skill helps interpret analysis reports and make timing closure decisions. For complete command syntax, see REFERENCE.md. For TCL execution, use vivado-tcl. For constraint changes, use vivado-constraints. For implementation strategies, use vivado-impl.
Timing Path Fundamentals
Four common path types:
1. Input Port → Register (constrained by set_input_delay)
2. Register → Register (constrained by clock period)
3. Register → Output Port (constrained by set_output_delay)
4. Input Port → Output Port (combinational, set_max_delay)Path structure (three sections):
Source Clock Path → Data Path → Destination Clock Path
(clock source (launch pin (clock source
to launch cell) to capture to capture
cell input) cell)Slack formula:
- Max delay (Setup/Recovery):
slack = data_required_time - data_arrival_time - Min delay (Hold/Removal):
slack = data_arrival_time - data_required_time
Max/Min Delay Analysis Corner Selection
| Analysis Type | Source Clock | Data Path | Destination Clock |
|---|---|---|---|
| Setup/Recovery (max delay) | Slow_max | Slow_max | Slow_min |
| Setup/Recovery (max delay) | Fast_max | Fast_max | Fast_min |
| Hold/Removal (min delay) | Slow_min | Slow_min | Slow_max |
| Hold/Removal (min delay) | Fast_min | Fast_min | Fast_max |
Key rule: Delays from different corners are NEVER mixed on same path during slack calculation.
Report Selection Guide
| Goal | Command | When to Use |
|---|---|---|
| Quick timing signoff | report_timing_summary | After implementation, mandatory before bitstream |
| Analyze specific paths | report_timing -from/-to/-through | Debugging specific failing paths |
| Overall QoR score (1-5) | report_qor_assessment | After routing, assess closure likelihood |
| Auto optimization hints | report_qor_suggestions | When stuck on timing closure |
| Path characteristics | report_design_analysis | Deep analysis of logic levels, fanout, physical spread |
| Methodology compliance | report_methodology | Early in flow to catch methodology violations |
| Resource usage | report_utilization | After synthesis or implementation |
| CDC checks | report_cdc | After synthesis, verify clock domain crossings |
| Congestion analysis | report_design_analysis -congestion | After placement, if timing degraded |
| Design rule checks | report_drc | Before bitstream generation |
| Bus skew | report_bus_skew | If set_bus_skew constraints exist (NOT in report_timing_summary) |
Timing Report Header Fields
| Field | Meaning |
|---|---|
| Slack | Positive = meets timing. Negative = violation |
| Source | Startpoint cell + launch clock (edge, name, period) |
| Destination | Endpoint cell + capture clock (edge, name, period) |
| Path Group | Clock group containing endpoint (async pins → async_default) |
| Path Type | Max (setup/recovery) or Min (hold/removal); corner (Slow/Fast) |
| Requirement | Clock period (same clock) or smallest positive delta (different clocks) |
| Data Path Delay | Total delay through logic section |
| Logic Levels | Count of each primitive type in data path |
| Clock Path Skew | Destination - Source insertion delay + CPR |
| CPR | Clock Pessimism Removal — shared clock circuitry correction |
| Clock Uncertainty | TSJ + TIJ + DJ + PE + UU (see below) |
Clock Uncertainty Components
| Component | Source |
|---|---|
| TSJ (Total System Jitter) | Combined system jitter on both clocks |
| TIJ (Total Input Jitter) | From set_input_jitter constraint |
| DJ (Discrete Jitter) | Hardware primitives (MMCM/PLL) |
| PE (Phase Error) | Phase variation between clock signals |
| UU (User Uncertainty) | From set_clock_uncertainty constraint |
Delay Type in Path Details
| Value | Meaning |
|---|---|
| Unplaced | Cell not placed, delay estimated |
| Estimated | Cell placed but not routed |
| Routed | Final routed delay |
Clock Phase Shift Mode (Device Defaults)
| Device Family | Default Mode | Behavior |
|---|---|---|
| 7 Series | WAVEFORM | Modifies clock waveform edges |
| UltraScale | WAVEFORM | Modifies clock waveform edges |
| UltraScale+ | LATENCY | Models as MMCM/PLL insertion delay |
| Versal | LATENCY | Models as MMCM/PLL insertion delay |
Warning: Migrating 7 Series/UltraScale designs to UltraScale+ changes phase shift modeling. Review and remove legacy multicycle path constraints used for phase shift.
QoR Assessment Interpretation (report_qor_assessment)
Score Meaning
| Score | Interpretation | Action |
|---|---|---|
| 1 | Design will likely NOT complete implementation | Major redesign needed |
| 2 | Will complete but will NOT meet timing | Significant optimization required |
| 3 | Will likely NOT meet timing | Targeted optimization needed |
| 4 | Will likely meet timing | Minor adjustments may suffice |
| 5 | Favorable timing-closure assessment | Perform final verification; generate a bitstream only if it is part of the requested deliverable and the applicable checks pass |
Five Assessment Categories
| Category | What It Checks |
|---|---|
| Utilization | Resource usage across device, SLR, Pblock levels |
| Netlist | Logical structure, DONT_TOUCH properties, high fanout nets |
| Clocking | Clock skew on setup and hold paths |
| Congestion | Netlist structures causing routing congestion |
| Timing | WNS/TNS/WHS/THS per clock group, net/LUT budget |
Each shows OK or REVIEW status. Items with asterisk (*) don't directly affect score but impact closure.
A QoR score predicts closure likelihood; it does not replace checks on the final design. For closure requests, use the full timing acceptance criteria, including constraint coverage and applicable bus-skew, CDC, DRC, and methodology checks. For report-only requests, explain the evidence and any verification gaps without automatically starting implementation or bitstream generation.
ML Strategy Availability
Available when ALL conditions met:
- opt_design ran with Explore or Default directive
- phys_opt_design enabled
- Design fully routed
- UltraScale or UltraScale+ device family
Auto-Termination
Set MIN_RQA_SCORE property (1-5) to auto-terminate runs scoring below threshold.
Show full SKILL.md (445 more words)Show less
QoR Suggestions Workflow
report_qor_suggestions ← Generate suggestions
↓
write_qor_suggestions file.rqs ← Export to file
↓
read_qor_suggestions file.rqs ← Import in next run
↓
Suggestions auto-apply ← If AUTOMATIC=YesSuggestion Classification
| Dimension | Values |
|---|---|
| Origin | GENERATED (current run) / EXISTING (imported from .rqs) |
| Status | APPLIED / FAILED TO APPLY |
| Stage generated | opt_design / place_design / phys_opt_design / route_design |
| Stage applicable | Where suggestion should be applied |
| Automatic | Yes (auto-apply) / No (manual action needed) |
Suggestion Categories
Clocking, Congestion, Utilization, Timing, Netlist, XDC, Strategy
Design Analysis Interpretation (report_design_analysis)
Timing Path Characteristics — Five Categories
| Category | Fields |
|---|---|
| Timing | Path Type, Requirement, Slack, Timing Exception |
| Logic | Start/End Pin Primitives, Pins, Logic Levels, Routes |
| Physical | Arch Boundary Crossings (IO/RAM/DSP/NOC), Pblock restrictions, Bounding Box, Net Fanout/Detour |
| Property | Combined LUT pairs, MARK_DEBUG, DONT_TOUCH, Fixed constraints |
| DFX | DFX Path Type, Boundary Nets, Boundary Fanout |
Complexity (Rent Exponent) Interpretation
| Rent Exponent | Complexity | Action |
|---|---|---|
| < 0.65 | Low to Normal | No action needed |
| 0.65 - 0.85 | High | Review hierarchy, consider floorplanning |
| > 0.85 | Very High | Redesign hierarchy, reduce connectivity |
Average Fanout: < 4 normal, 4-5 placement difficulty, > 5 implementation failure risk.
Congestion Level Interpretation
| Level | Impact | Action |
|---|---|---|
| 3-4 | Minor | Usually acceptable unless timing budget is tight |
| 5+ | Significant QoR impact | Apply congestion mitigation strategies |
Timing Closure Decision Tree
Setup Violation Resolution
Setup violation detected
├─ Check Logic Levels (report_design_analysis)
│ └─ High logic levels → Pipeline registers / retiming (vivado-synth: -global_retiming)
├─ Check Fanout (report_design_analysis)
│ └─ High fanout → MAX_FANOUT attribute / phys_opt replication (vivado-impl)
├─ Check Physical Spread (report_design_analysis -congestion)
│ └─ Large bounding box → Pblock floorplanning (vivado-constraints)
├─ Check Clock Skew
│ └─ Negative skew → Review clock tree, BUFG placement
└─ Check Timing Exception
└─ Missing/wrong constraint → Fix in XDC (vivado-constraints)Hold Violation Resolution
Hold violation detected
├─ Check fast-corner delay
│ └─ Very short data path → Add delay cells (phys_opt_design hold fix)
├─ Check Clock Skew
│ └─ Large positive skew → Review clock tree balance
└─ Check Inter-SLR paths (SSI devices)
└─ SLR crossing → SLR-aware placement (vivado-impl)Congestion Mitigation
Congestion Level ≥ 5
├─ Check utilization (report_utilization)
│ └─ > 80% LUT → Reduce design size or use area-optimized synthesis
├─ Check high-fanout nets
│ └─ Replicate drivers (phys_opt_design fanout optimization)
├─ Try congestion-focused strategies
│ └─ vivado-impl: Congestion_* strategies
└─ Floorplanning
└─ Spread logic across device (Pblocks, vivado-constraints)Message Severity Levels
| Severity | Meaning | Action Required |
|---|---|---|
| Status | General processing feedback | None |
| Info | Process/design feedback | None |
| Warning | Constraints not applied as intended, sub-optimal results possible | Review |
| Critical Warning | Input/constraints failing best practices, often leads to errors | Fix recommended |
| Error | Problem stopping design flow | Must fix |
Tip: Promote warning severity: set_msg_config -id "Common 17-81" -new_severity "CRITICAL WARNING"
Design Check Waiver System
When to Waive
- Known-safe CDC crossings with external synchronization
- DRC checks not applicable to your design
- Methodology checks overridden by design intent
Waiver Wildcards
| Keyword | Matches |
|---|---|
*CELL | Any cell |
*NET | Any net |
*PIN | Any pin |
*PORT | Any port |
*CLOCK | Any clock |
* | Any string |
Waivers auto-saved in checkpoints. Export with write_waivers, import with read_xdc or source.
Cannot delete AMD IP waivers.
Synthesis Analysis & Closure Techniques
RTL Optimization: Integer Range Constraints
Explicitly define signal ranges to reduce logic depth:
// Before: 32-bit counter, deep comparator logic
reg [31:0] counter;
// After: range-constrained, smaller comparator
reg [9:0] counter; // if max value < 1024Deep Memory Decomposition
| Attribute | Purpose | Effect |
|---|---|---|
| RAM_DECOMP | Control memory decomposition strategy | power vs area tradeoff |
| CASCADE_HEIGHT | Granular cascading depth control | Limits BRAM cascade chain depth |
RAMB Utilization (Non-Power-of-2 Depth)
When memory depth is not a power of 2, synthesis may over-allocate BRAMs. Manually partition with address decoder for optimal utilization. Check report_utilization and synthesis log for memory mapping.
RAMB Output Register Inference
Multiple logic levels before BRAM output flip-flop prevent DOA register inference → timing degradation. Restructure RTL to allow BRAM output register usage (see vivado-impl examples/ug906/ for before/after).
Configurable Report Strategies
| Strategy | Stage | Focus |
|---|---|---|
| Vivado Synthesis Default | Synthesis | Utilization only |
| Vivado Implementation Default | Implementation | Standard reports |
| UltraFast Methodology Reports | Implementation | Methodology compliance |
| Performance Explore Reports | Implementation | Timing exploration |
| Timing Closure Reports | Implementation | Detailed timing analysis |
| No Reports | Both | Skip all reports |
© Shinei-Nouzen-Arch, GPL-2.0. Rendered from Markdown: HTML in the file is shown as text, images as links, and headings moved down two levels. Raw file
Files
SKILL.md and 2 other files in vivado-analysis of Shinei-Nouzen-Arch/FPGA-Agent.
- SKILL.md
- REFERENCE.md
- agents/openai.yaml
Open the folder on GitHubat commit b60a52e
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| Typescript Advanced Typesrolling-scopes/rsschool-app | 10k | 25 repos | ~4.2k | Automated safety check: Pass | MPL-2.0 | |
| PR Babysitteropeninterpreter/openinterpreter | 69k | 3 repos | ~4.2k | Automated safety check: Pass | Apache-2.0 | |
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Questions about Vivado Analysis
What does Vivado Analysis do?
A skill your agent uses when the user needs Vivado design analysis, timing report interpretation, or timing-closure diagnosis. Vivado Analysis is an agent skill from Shinei-Nouzen-Arch/FPGA-Agent. Use this skill when the user needs Vivado design analysis, timing report interpretation, or timing-closure diagnosis.
When should I use Vivado Analysis?
Vivado Analysis fits situations like: the user needs Vivado design analysis; timing report interpretation; timing-closure diagnosis.
How do I install Vivado Analysis in Claude Code?
Run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-analysis -a claude-code`. Or copy the skill folder (vivado-analysis in Shinei-Nouzen-Arch/FPGA-Agent) into .claude/skills/vivado-analysis in your project. Claude Code loads it when a task matches its description.
How do I install Vivado Analysis in Codex?
Run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-analysis -a codex`. Or copy the skill folder (vivado-analysis in Shinei-Nouzen-Arch/FPGA-Agent) into .agents/skills/vivado-analysis in your project. Codex loads it when a task matches its description.
Can I use Vivado Analysis in Cursor, Gemini CLI or GitHub Copilot?
Cursor, Gemini CLI, GitHub Copilot and OpenCode also load SKILL.md folders. With the skills CLI, run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-analysis -a cursor` (or -a gemini-cli, github-copilot or opencode for the others). To copy it by hand, put the folder in .cursor/skills/vivado-analysis, .gemini/skills/vivado-analysis, .github/skills/vivado-analysis and .opencode/skills/vivado-analysis in your project.
What does Vivado Analysis need to run?
SKILL.md names no scripts, command-line tools or credentials: Vivado Analysis is instructions for the agent only.
Does Vivado Analysis access the network?
SKILL.md contains no URLs. Any network use would come from the scripts or tools the agent runs. This is read from the text; nothing was executed.
Is Vivado Analysis safe to install?
Our automated static check of SKILL.md found no risky patterns, such as piping downloads into a shell, reading credential files or hidden Unicode. It is not a guarantee. Review the folder before installing.
What licence does Vivado Analysis use?
Vivado Analysis is published under the GPL-2.0 licence (the repository's licence). It allows redistribution, so the full SKILL.md is shown on this page.
How many tokens does Vivado Analysis use?
About 3.3k tokens (SKILL.md is roughly 13k characters). Agents keep only the skill's name and description in context until a task matches; then they load SKILL.md in full.
What are the alternatives to Vivado Analysis?
Skills that share tags, products or a category with Vivado Analysis: Vercel Composition Patterns (supabase/supabase, 111k stars), Finishing a Development Branch (obra/superpowers, 297k stars), Typescript Advanced Types (rolling-scopes/rsschool-app, 10k stars) and PR Babysitter (openinterpreter/openinterpreter, 69k stars). The comparison table on this page puts their stars, adoption, token cost, safety result and licence side by side.
Who maintains Vivado Analysis?
Shinei-Nouzen-Arch (a GitHub user) maintains it in Shinei-Nouzen-Arch/FPGA-Agent, which has 180 GitHub stars. The repository holds 10 skills in this directory. The repository was last updated on September 5, 2026.
Source: Shinei-Nouzen-Arch/FPGA-Agent on GitHub. Facts on this page come from the repository at the commit we read; the author's words are quoted as theirs.