Agent skill

Vivado Synth

by Shinei-Nouzen-Arch in Shinei-Nouzen-Arch/FPGA-Agent

A skill your agent uses when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synthdesign option tuning, resource inference control…

GPL-2.0Auto-check passedDevelopment

Install Vivado Synth

skills CLI

$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-synth -a claude-code

Project install by default; add -g for ~/.claude/skills/.

GitHub CLI

$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-synth --agent claude-code

Project scope by default; add --scope user for a personal install. Needs GitHub CLI 2.90.0 or later (public preview).

Manual copy

$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .claude/skills && cp -r skills-src/vivado-synth .claude/skills/vivado-synth && rm -rf skills-src

Use ~/.claude/skills/ instead of .claude/skills for a personal install. The folder must contain SKILL.md.

Claude Code skills documentation · loads skills from .claude/skills/

Paste into Claude Code

Install the "vivado-synth" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-synth into .claude/skills/vivado-synth/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-synth", then confirm the skill loads.

Claude Code copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.

$skill-installer

$skill-installer install https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-synth

Type this inside Codex. $skill-installer <name> installs a curated skill from openai/skills. The installer writes to $CODEX_HOME/skills (default ~/.codex/skills). Restart Codex if the skill does not show up.

skills CLI

$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-synth -a codex

Project install goes to .agents/skills/; add -g for ~/.codex/skills/.

GitHub CLI

$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-synth --agent codex

Project scope by default (.agents/skills/); add --scope user for a personal install.

Manual copy

$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .agents/skills && cp -r skills-src/vivado-synth .agents/skills/vivado-synth && rm -rf skills-src

Use ~/.agents/skills/ instead of .agents/skills for a personal install.

Codex skills documentation · loads skills from .agents/skills/

Paste into Codex

Install the "vivado-synth" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-synth into .agents/skills/vivado-synth/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-synth", then confirm the skill loads.

Codex copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.

skills CLI

$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-synth -a cursor

Project install goes to .agents/skills/; add -g for ~/.cursor/skills/.

GitHub CLI

$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-synth --agent cursor

Project scope by default (.agents/skills/); add --scope user for a personal install.

Manual copy

$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .cursor/skills && cp -r skills-src/vivado-synth .cursor/skills/vivado-synth && rm -rf skills-src

Use ~/.cursor/skills/ instead of .cursor/skills for a personal install.

Cursor skills documentation · loads skills from .cursor/skills/, .agents/skills/, .claude/skills/, .codex/skills/

Paste into Cursor

Install the "vivado-synth" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-synth into .cursor/skills/vivado-synth/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-synth", then confirm the skill loads.

Cursor copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.

gemini skills install

$ gemini skills install https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git --path vivado-synth

--scope user (default) or --scope workspace; --path is the subfolder of the repo that holds the skill; --consent skips the security confirmation prompt.

skills CLI

$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-synth -a gemini-cli

Project install goes to .agents/skills/; add -g for ~/.gemini/skills/.

GitHub CLI

$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-synth --agent gemini-cli

Project scope by default (.agents/skills/); add --scope user for a personal install.

Manual copy

$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .gemini/skills && cp -r skills-src/vivado-synth .gemini/skills/vivado-synth && rm -rf skills-src

Use ~/.gemini/skills/ instead of .gemini/skills for a personal install, then run /skills reload.

Gemini CLI skills documentation · loads skills from .gemini/skills/, .agents/skills/

Paste into Gemini CLI

Install the "vivado-synth" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-synth into .gemini/skills/vivado-synth/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-synth", then confirm the skill loads.

Gemini CLI copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.

GitHub CLI

$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-synth

Installs for Copilot at project scope by default; add --scope user for a personal install. Preview a skill first with gh skill preview. Needs GitHub CLI 2.90.0 or later (public preview).

skills CLI

$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-synth -a github-copilot

Project install goes to .agents/skills/; add -g for ~/.copilot/skills/.

Manual copy

$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .github/skills && cp -r skills-src/vivado-synth .github/skills/vivado-synth && rm -rf skills-src

Use ~/.copilot/skills/ instead of .github/skills for a personal install. Commit .github/skills so cloud agent and code review can use it.

GitHub Copilot skills documentation · loads skills from .github/skills/, .claude/skills/, .agents/skills/

Paste into GitHub Copilot

Install the "vivado-synth" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-synth into .github/skills/vivado-synth/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-synth", then confirm the skill loads.

GitHub Copilot copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.

skills CLI

$ npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-synth -a opencode

OpenCode documents no install command of its own. Project install goes to .agents/skills/; add -g for ~/.config/opencode/skills/.

GitHub CLI

$ gh skill install Shinei-Nouzen-Arch/FPGA-Agent vivado-synth --agent opencode

Project scope by default (.agents/skills/); add --scope user for a personal install.

Manual copy

$ git clone --depth 1 https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git skills-src && mkdir -p .opencode/skills && cp -r skills-src/vivado-synth .opencode/skills/vivado-synth && rm -rf skills-src

Use ~/.config/opencode/skills/ instead of .opencode/skills for a personal install.

OpenCode skills documentation · loads skills from .opencode/skills/, .claude/skills/, .agents/skills/

Paste into OpenCode

Install the "vivado-synth" agent skill from https://github.com/Shinei-Nouzen-Arch/FPGA-Agent/tree/main/vivado-synth into .opencode/skills/vivado-synth/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "vivado-synth", then confirm the skill loads.

OpenCode copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.

Facts

Skill name: vivado-synth
GitHub stars: 180
Token cost: ~3.6k tokens
SKILL.md length: 1,260 words
Files: 67
Skills in repo: 10
Repo updated: Sep 5, 2026
First seen: Oct 7, 2026
Licence: GPL-2.0

At a glance

A skill your agent uses when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synthdesign option tuning, resource inference control…

The user needs help with Vivado synthesis strategy selection
SKILL.md covers synth_design Complete Options, Strategy Decision Table, Synthesis Attributes Quick… and Block-Level Synthesis…, plus 5 more sections
Instructions only: no scripts, shell commands, URLs or credentials in SKILL.md
Synthesis attribute configuration

What it does

Vivado Synth is an agent skill from Shinei-Nouzen-Arch/FPGA-Agent. Use this skill when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synthdesign option tuning, resource inference control (RAM/DSP/SRL/BRAM), hierarchy optimization (flattenhierarchy, KEEPHIERARCHY), OOC (out-of-context) synthesis, incremental synthesis, RTL linting, Block-Level synthesis (BLOCKSYNTH), or any synthesis optimization decision. Trigger when the user mentions synthesis strategies, synthesis directives, synthesis attributes, resource mapping control…

Its SKILL.md is about 3.6k tokens, which your agent loads only when the skill is triggered. The skill folder holds 68 other files (for example `REFERENCE.md` and `agents/openai.yaml`).

It sits in Development, covering Linting and formatting. The licence is GPL-2.0.

When your agent uses it

The user needs help with Vivado synthesis strategy selection
Synthesis attribute configuration
Synthdesign option tuning
Resource inference control (RAM/DSP/SRL/BRAM)

Example prompts

“/vivado-synth”

What it can do on your machine

Read from SKILL.md and the folder at commit b60a52e. It shows what the files ask for, not the result of running them.

Tool permissions
Pre-approves nothing: there is no allowed-tools line, so your agent's usual permission prompts apply.
From allowed-tools in the SKILL.md frontmatter.
Runs code
No scripts in the folder and no shell commands in SKILL.md (its code samples are tcl).
From the folder's file list and the shell code blocks in SKILL.md.
Network
No URLs in SKILL.md.
From URLs in SKILL.md, links to its own repository left out.
Credentials
Names no API keys, tokens, secrets or passwords.
From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.

Context cost

Vivado Synth loads about 3.6k tokens when it runs. Until then it costs about 180 tokens; SKILL.md has 1,260 words of instructions outside code blocks.

Always · name and description, kept in context so the agent knows when to use it: ~180
When it runs · the whole SKILL.md, loaded when a task matches: ~3.6k

Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.

Safety

Auto-check passed

The automated check found no risky patterns in SKILL.md.

Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.

SKILL.md

The full file from Shinei-Nouzen-Arch/FPGA-Agent at commit b60a52e, republished under its GPL-2.0 licence (© Shinei-Nouzen-Arch). 1,260 words, ~3,569 tokens.

Download SKILL.mdSave it as .claude/skills/vivado-synth/SKILL.md (or your agent's skills folder). This skill also uses 66 other files; get the full folder from GitHub.

name: vivado-synth
description: Use this skill when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synth_design option tuning, resource inference control (RAM/DSP/SRL/BRAM), hierarchy optimization (flatten_hierarchy, KEEP_HIERARCHY), OOC (out-of-context) synthesis, incremental synthesis, RTL linting, Block-Level synthesis (BLOCK_SYNTH), or any synthesis optimization decision. Trigger when the user mentions synthesis strategies, synthesis directives, synthesis attributes, resource mapping control, FSM encoding, retiming, or asks how to optimize synthesis results for area/timing/power. This skill provides decision-making knowledge — for TCL command execution, use vivado-tcl skill.

Vivado Synthesis Decision Guide

Based on UG901 (v2025.2). This skill helps choose the right synthesis strategies, options, and attributes. For attribute syntax see REFERENCE.md; for HDL coding templates (RAM/DSP/ROM/SRL/FSM/etc.) see examples/ directory — consult the index table in REFERENCE.md to locate the right file.

synth_design Complete Options

Hierarchy Control

Option	Values	Default	Effect
`-flatten_hierarchy`	none/full/rebuilt	rebuilt	none: preserve RTL hierarchy. full: flatten to top only. rebuilt: flatten then rebuild similar hierarchy (best QoR + readability)

Timing Optimization

Option	Values	Default	Effect
`-directive`	See strategy table below	Default	Selects preconfigured optimization strategy
`-global_retiming`	auto/on/off	auto	Register balancing across combinational logic. Auto = on for Versal, off for others
`-no_timing_driven`	flag	—	Disables timing-driven synthesis (faster, worse timing)

Resource Control

Option	Values	Default	Effect
`-max_bram`	integer	-1 (max)	Limit Block RAM usage
`-max_uram`	integer	-1 (max)	Limit UltraRAM usage (UltraScale+)
`-max_dsp`	integer	-1 (max)	Limit DSP block usage
`-shreg_min_size`	integer	3	Min chain length for SRL inference
`-srl_style`	register/rl/srl_reg/reg_srl/reg_srl_reg	—	Global SRL implementation style
`-cascade_dsp`	auto/tree/force	auto	DSP adder chain implementation
`-max_bram_cascade_height`	integer	-1	Max BRAM cascade depth
`-max_uram_cascade_height`	integer	-1	Max UltraRAM cascade depth
`-no_srlextract`	flag	—	Disable all SRL extraction
`-no_lc`	flag	—	Disable LUT combining

FSM & Logic

Option	Values	Default	Effect
`-fsm_extraction`	auto/one_hot/sequential/gray/johnson/user_encoding/off	auto	FSM encoding strategy
`-resource_sharing`	auto/on/off	auto	Arithmetic operator sharing
`-keep_equivalent_registers`	flag	off	Prevent merging of equivalent registers
`-control_set_opt_threshold`	auto/integer/0	auto	Fanout threshold for control set optimization. 0 = disable

Clock & IO

Option	Values	Default	Effect
`-bufg`	integer	12	Max global clock buffers to infer
`-gated_clock_conversion`	off/on/auto	off	Convert gated clocks to enables

Design Entry

Option	Values	Default	Effect
`-top`	module name	—	Top module
`-part`	part number	—	Target FPGA part
`-constrset`	fileset name	—	Constraint fileset to use
`-include_dirs`	paths	—	Verilog include search dirs
`-generic`	name=value	—	Override Verilog parameters / VHDL generics
`-verilog_define`	macro[=text]	—	Define Verilog macros
`-mode`	default/out_of_context	default	OOC mode: no IO buffers

Special Modes

Option	Values	Default	Effect
`-rtl`	flag	—	Elaborate only, don't synthesize
`-lint`	flag	—	Run RTL Linter only (see section below)
`-incremental_mode`	default/quick/off	default	Incremental synthesis mode
`-sfcu`	flag	—	Single-file compilation unit mode

Debug & Performance

Option	Values	Default	Effect
`-debug_log`	flag	—	Extra debug info in log
`-assert`	flag	—	Enable VHDL assertions

Multi-Threading

tcl

set_param general.maxThreads 8  ;# 1-8 threads for synthesis

Strategy Decision Table

Use -directive <strategy> to select:

Scenario	Strategy	Key Effect
Default / first try	`default`	Balanced optimization
Fast iteration / debug	`runtimeoptimized`	Fewer optimizations, faster runtime
Resource-constrained	`AreaOptimized_high`	Force ternary adders, includes AreaMapLargeShiftRegToBRAM + AreaMultThresholdDSP
Resource-constrained (moderate)	`AreaOptimized_medium`	Area-optimized MUX, ternary adders, lower multiplier→DSP threshold
Timing-critical	`PerformanceOptimized`	Logic level reduction at expense of area
Routing congestion	`AlternateRoutability`	Less MUXF/CARRY usage for better routability
Minimum area	`LogicCompaction`	Compact CARRY+LUT into fewer SLICEs (negative timing impact)
DSP-heavy	`AreaMultThresholdDSP`	Lower threshold for multiplier→DSP inference
Carry-chain issues	`FewerCarryChains`	Higher threshold to use LUTs instead of carry chains
Large shift registers	`AreaMapLargeShiftRegToBRAM`	Implement large shift regs in Block RAM

Note: Directive values are case-sensitive in v2025.2. Use exactly as shown above.

Synthesis Attributes Quick Reference (by scenario)

Preventing Optimization

Attribute	Values	Where	When to Use
`DONT_TOUCH`	TRUE/FALSE	RTL+XDC	Prevent optimization AND preserve through P&R. Strongest protection
`KEEP`	TRUE/FALSE	RTL only	Prevent signal absorption into LUTs. Synthesis-only, NOT forwarded to P&R
`KEEP_HIERARCHY`	TRUE/SOFT/FALSE	RTL+XDC	SOFT (recommended): allow constant propagation. TRUE: block all cross-boundary optimization

Resource Inference Control

Attribute	Values	Where	When to Use
`RAM_STYLE`	block/distributed/registers/ultra/mixed/auto	RTL+XDC	Force specific RAM implementation
`ROM_STYLE`	block/distributed/ultra	RTL+XDC	Force specific ROM implementation
`USE_DSP`	yes/no/logic/simd	RTL+XDC	Force/prevent DSP block usage. `logic`=XOR→DSP, `simd`=SIMD mode
`SHREG_EXTRACT`	yes/no	RTL+XDC	Enable/disable SRL inference
`SRL_STYLE`	register/srl/srl_reg/reg_srl/reg_srl_reg/block	RTL+XDC	Specific SRL implementation
`RAM_DECOMP`	power/area	RTL+XDC	RAM split: `power` = address decode (saves power), `area` = smallest
`CASCADE_HEIGHT`	integer (0=disable)	RTL+XDC	BRAM/URAM cascade chain length (UltraScale+ only)
`RW_ADDR_COLLISION`	auto/yes/no	RTL only	Read-write collision handling

Timing Optimization

Attribute	Values	Where	When to Use
`RETIMING_FORWARD`	integer (0=off)	RTL+XDC	Move register forward through logic
`RETIMING_BACKWARD`	integer (0=off)	RTL+XDC	Move register backward through logic
`CRITICAL_SIG_OPT`	true/false	RTL+XDC	Shannon decomposition on critical feedback loops. Trades area for timing
`MAX_FANOUT`	integer (-1=no limit)	RTL+XDC	Fanout limit → triggers register replication. Best on local signals only

Debug

Attribute	Values	Where	When to Use
`MARK_DEBUG`	TRUE/FALSE	RTL+XDC	Mark nets for ILA debug probing
`ASYNC_REG`	TRUE/FALSE	RTL+XDC	Mark CDC synchronizer registers

FSM

Attribute	Values	Where	When to Use
`FSM_ENCODING`	one_hot/sequential/gray/johnson/user_encoding/none	RTL+XDC	Override FSM encoding
`FSM_SAFE_STATE`	auto_safe_state/reset_state/power_on_state/default_state	RTL+XDC	Add invalid state recovery logic

IO & Clock

Attribute	Values	Where	When to Use
`IOB`	TRUE/FALSE	RTL only	Pack register into IOB
`IO_BUFFER_TYPE`	NONE	RTL only	Disable automatic IO buffer insertion
`CLOCK_BUFFER_TYPE`	BUFG/BUFH/BUFIO/BUFMR/BUFR/none	RTL+XDC	Specify clock buffer type
`GATED_CLOCK`	yes	RTL+XDC	Mark signal as clock for gated clock conversion

Show full SKILL.md (527 more words)Show less

Enable & Reset

Attribute	Values	Where	When to Use
`DIRECT_ENABLE`	yes	RTL+XDC	Force signal to CE pin of register
`DIRECT_RESET`	yes	RTL+XDC	Force signal to reset pin of register
`EXTRACT_ENABLE`	yes/no	RTL+XDC	Control enable extraction to CE pin
`EXTRACT_RESET`	yes/no	RTL+XDC	Control reset extraction (sync reset only)

DSP Folding

Attribute	Values	Where	When to Use
`DSP_FOLDING`	yes/no	RTL only	Fold two MAC structures into one DSP
`DSP_FOLDING_FASTCLOCK`	yes/no	RTL only	Designate fast clock port for DSP folding

Verilog Case Control

Attribute	Values	Where	When to Use
`FULL_CASE`	(presence)	RTL only	All case values covered — suppress latch inference
`PARALLEL_CASE`	(presence)	RTL only	Build as parallel if-elsif, no priority

Other

Attribute	Values	Where	When to Use
`BLACK_BOX`	(presence)	RTL only	Force module to black box
`TRANSLATE_OFF/ON`	comment-based	RTL only	Exclude code from synthesis

Block-Level Synthesis (BLOCK_SYNTH)

Apply per-instance synthesis settings via XDC:

tcl

set_property BLOCK_SYNTH.<option> <value> [get_cells <instance>]

Option	Type	Values	Description
STRATEGY	STRING	DEFAULT/AREA_OPTIMIZED/ALTERNATE_ROUTABILITY/PERFORMANCE_OPTIMIZED	Per-instance strategy
RETIMING	INT	0/1	Enable/disable retiming
ADDER_THRESHOLD	INT	4-128	Adder size → CARRY chain threshold
COMPARATOR_THRESHOLD	INT	4-128	Comparator size → CARRY chain threshold
SHREG_MIN_SIZE	INT	3-32	SRL inference threshold
FSM_EXTRACTION	STRING	OFF/ONE_HOT/SEQUENTIAL/GRAY/JOHNSON/AUTO	FSM encoding
LUT_COMBINING	INT	0/1	Enable/disable LUT combining
CONTROL_SET_THRESHOLD	INT	0-128	Control set optimization threshold
MAX_LUT_INPUT	INT	4-6	4=no LUT5/6, 5=no LUT6, 6=all
MUXF_MAPPING	INT	0/1	Enable/disable MUXF7/F8/F9
KEEP_EQUIVALENT_REGISTER	INT	0/1	Merge or retain equivalent registers
PRESERVE_BOUNDARY	INT	any	Mark hierarchy as changing (for incremental)
LOGIC_COMPACTION	INT	1	Compact CARRY+LUT into fewer SLICEs
SRL_STYLE	STRING	REGISTER/SRL/SRL_REG/REG_SRL/REG_SRL_REG	SRL implementation

Note: BLOCK_SYNTH hardens the instance hierarchy. Use only where needed.

OOC (Out-of-Context) Synthesis

When to use: Large IP modules, 3rd-party netlists, modules that rarely change.

tcl

# Non-Project Mode
synth_design -top <module> -part <part> -mode out_of_context

# Project Mode: right-click module → Set As Out-of-Context for Synthesis

Key rules:

OOC modules are synthesized independently, treated as black boxes in top-level synthesis
No IO buffers are created
Incremental synthesis is NOT supported for OOC runs
Do NOT use OOC if module has AMD IP in lower levels
Do NOT use OOC if module ports use user-defined types

Incremental Synthesis

Detects RTL changes and only re-synthesizes modified sections. Reduces runtime and QoR fluctuation.

tcl

# Project Mode: Settings → Synthesis → Incremental synthesis
# Non-Project Mode:
synth_design -top <top> -part <part> -incremental_mode default

Mode	Effect
`default`	Full incremental (detect + selective re-synthesis)
`quick`	Faster, less thorough incremental
`off`	Full re-synthesis

Note: Not supported for OOC runs.

RTL Linter

Pre-synthesis code quality check:

tcl

synth_design -lint -top <top> -part <part>
# For OOC runs:
synth_design -lint -srcset [get_property SRCSET [get_runs my_IP_core_synth_1]]

Key rules detected: latch inference (INFER-1), combinational loops (INFER-4), arithmetic overflow (ASSIGN-1), mixed clock edges (CLOCK-1), mixed async resets (RESET-1), unconnected ports (ASSIGN-12). See REFERENCE.md for complete rule table.

Waivers:

tcl

create_waiver -type LINT -id ASSIGN-1 -rtl_hierarchy x/y
write_waivers -type LINT -file waivers.tcl

Synthesis-Stage Constraints

Only these constraints are used during synthesis:

Type	Commands
Timing	`create_clock`, `create_generated_clock`, `set_input_delay`, `set_output_delay`, `set_false_path`, `set_multicycle_path`, `set_max_delay`, `set_clock_groups`, `set_clock_latency`, `set_disable_timing`
Object Access	`all_clocks`, `all_inputs`, `all_outputs`, `get_cells`, `get_ports`, `get_clocks`, `get_nets`, `get_pins`

Important: Timing analysis on synthesized design uses estimated routing delays — only post-route timing is accurate.

Attribute Propagation Rules

Placing attribute on a hierarchy affects only its boundary, NOT signals inside (except: DSP_FOLDING, RAM_STYLE, ROM_STYLE, SHREG_EXTRACT, USE_DSP — these DO affect internal signals)
If same attribute is set in both RTL and XDC with different values → XDC wins
KEEP must be set in RTL; XDC does not support it.
DONT_TOUCH supports both RTL and XDC. Set it in RTL when the object may be optimized away before XDC is read. For existing applicable cells or nets, XDC can set or override the property without requiring an RTL edit. Preserve the user's requested modification scope.

Files

SKILL.md and 66 other files in vivado-synth of Shinei-Nouzen-Arch/FPGA-Agent.

SKILL.md
REFERENCE.md
agents/openai.yaml
examples/asym_ram_sdp_read_wider.v
examples/asym_ram_sdp_write_wider.v
examples/asym_ram_tdp_read_first.v
examples/asym_ram_tdp_write_first.v
examples/black_box_1.v
examples/bytewrite_ram_1b.v
examples/bytewrite_tdp_ram_nc.v
examples/bytewrite_tdp_ram_readfirst2.v
examples/bytewrite_tdp_ram_rf.v
examples/bytewrite_tdp_ram_wf.v
examples/cmacc.v
examples/cmult.v
examples/convergentRoundingEven.v
examples/convergentRoundingOdd.v
examples/dynamic_shift_registers_1.v
examples/dynpreaddmultadd.v
… and 48 more

Open the folder on GitHubat commit b60a52e

Compare with similar skills

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Questions about Vivado Synth

What does Vivado Synth do?

A skill your agent uses when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synthdesign option tuning, resource inference control…. Vivado Synth is an agent skill from Shinei-Nouzen-Arch/FPGA-Agent. Use this skill when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synthdesign option tuning, resource inference control (RAM/DSP/SRL/BRAM), hierarchy optimization (flattenhierarchy, KEEPHIERARCHY), OOC (out-of-context) synthesis, incremental synthesis, RTL linting, Block-Level synthesis (BLOCKSYNTH), or any synthesis optimization decision.

When should I use Vivado Synth?

Vivado Synth fits situations like: the user needs help with Vivado synthesis strategy selection; synthesis attribute configuration; synthdesign option tuning; resource inference control (RAM/DSP/SRL/BRAM).

How do I install Vivado Synth in Claude Code?

Run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-synth -a claude-code`. Or copy the skill folder (vivado-synth in Shinei-Nouzen-Arch/FPGA-Agent) into .claude/skills/vivado-synth in your project. Claude Code loads it when a task matches its description.

How do I install Vivado Synth in Codex?

Run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-synth -a codex`. Or copy the skill folder (vivado-synth in Shinei-Nouzen-Arch/FPGA-Agent) into .agents/skills/vivado-synth in your project. Codex loads it when a task matches its description.

Can I use Vivado Synth in Cursor, Gemini CLI or GitHub Copilot?

Cursor, Gemini CLI, GitHub Copilot and OpenCode also load SKILL.md folders. With the skills CLI, run `npx skills add Shinei-Nouzen-Arch/FPGA-Agent --skill vivado-synth -a cursor` (or -a gemini-cli, github-copilot or opencode for the others). To copy it by hand, put the folder in .cursor/skills/vivado-synth, .gemini/skills/vivado-synth, .github/skills/vivado-synth and .opencode/skills/vivado-synth in your project.

What does Vivado Synth need to run?

SKILL.md names no scripts, command-line tools or credentials: Vivado Synth is instructions for the agent only.

Does Vivado Synth access the network?

SKILL.md contains no URLs. Any network use would come from the scripts or tools the agent runs. This is read from the text; nothing was executed.

Is Vivado Synth safe to install?

Our automated static check of SKILL.md found no risky patterns, such as piping downloads into a shell, reading credential files or hidden Unicode. It is not a guarantee. Review the folder before installing.

What licence does Vivado Synth use?

Vivado Synth is published under the GPL-2.0 licence (the repository's licence). It allows redistribution, so the full SKILL.md is shown on this page.

How many tokens does Vivado Synth use?

About 3.6k tokens (SKILL.md is roughly 14k characters). Agents keep only the skill's name and description in context until a task matches; then they load SKILL.md in full.

What are the alternatives to Vivado Synth?

Skills that share tags, products or a category with Vivado Synth: Minimizing Ty Ecosystem Changes (astral-sh/ruff, 50k stars), Install Anti-Slop Oxlint Rules (dmmulroy/anti-slop, 5.4k stars), Babysit PR To Pass CI (sgl-project/sglang, 37k stars) and Rust Best Practices (farm-fe/farm, 5.6k stars). The comparison table on this page puts their stars, adoption, token cost, safety result and licence side by side.

Who maintains Vivado Synth?

Shinei-Nouzen-Arch (a GitHub user) maintains it in Shinei-Nouzen-Arch/FPGA-Agent, which has 180 GitHub stars. The repository holds 10 skills in this directory. The repository was last updated on September 5, 2026.

Source: Shinei-Nouzen-Arch/FPGA-Agent on GitHub. Facts on this page come from the repository at the commit we read; the author's words are quoted as theirs.

Install Vivado Synth

Facts

At a glance

What it does

When your agent uses it

Example prompts

What it can do on your machine

Tool permissions

Runs code

Network

Credentials

Context cost

Safety

SKILL.md

Vivado Synthesis Decision Guide

synth_design Complete Options

Hierarchy Control

Timing Optimization

Resource Control

FSM & Logic

Clock & IO

Design Entry

Special Modes

Debug & Performance

Multi-Threading

Strategy Decision Table

Synthesis Attributes Quick Reference (by scenario)

Preventing Optimization

Resource Inference Control

Timing Optimization

Debug

FSM

IO & Clock

Enable & Reset

DSP Folding

Verilog Case Control

Other

Block-Level Synthesis (BLOCK_SYNTH)

OOC (Out-of-Context) Synthesis

Incremental Synthesis

RTL Linter

Synthesis-Stage Constraints

Attribute Propagation Rules

Files

Compare with similar skills

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Questions about Vivado Synth