Vitis Hls Synthesis

What it does

When your agent uses it

• Development work in your project

Example prompts

• “/vitis-hls-synthesis”

Requirements

• Python 3

Workflow steps

10 steps, taken from the step headings in SKILL.md.

1. 1Project Initialization
2. 2Code Development
3. 3Configuration File
4. 4Run Flow
5. 5Report Analysis
6. 6Pipeline Optimization Kernel
7. 7Array Partition Optimization
8. 8Dataflow Task Parallelism
9. 9AXI4-Stream Interface
10. 10Fixed-Point Conversion

What it can do on your machine

Read from SKILL.md and the folder at commit b60a52e. It shows what the files ask for, not the result of running them.

• Tool permissions

  Pre-approves nothing: there is no allowed-tools line, so your agent's usual permission prompts apply.

  From allowed-tools in the SKILL.md frontmatter.

• Runs code

  Ships script files (Python, from the files we listed), which the agent can run.

  From the folder's file list and the shell code blocks in SKILL.md.

• Network

  No URLs in SKILL.md.

  From URLs in SKILL.md, links to its own repository left out.

• Credentials

  Names no API keys, tokens, secrets or passwords.

  From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.

Context cost

Vitis Hls Synthesis loads about 1.8k tokens when it runs. Until then it costs about 78 tokens; SKILL.md has 655 words of instructions outside code blocks.

Always · name and description, kept in context so the agent knows when to use it

~78

When it runs · the whole SKILL.md, loaded when a task matches

~1.8k

Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.

Safety

Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.

SKILL.md

The full file from Shinei-Nouzen-Arch/FPGA-Agent at commit b60a52e, republished under its GPL-2.0 licence (© Shinei-Nouzen-Arch). 655 words, ~1,820 tokens.

name

vitis-hls-synthesis

description

Vitis HLS synthesis assistant for C/C++ to RTL conversion. Covers kernel development, pragma optimization, interface configuration, and synthesis report analysis. For post-synthesis implementation use vivado-impl, for timing analysis use vivado-analysis, for hardware debug use vivado-debug.

mkdir -p <project>/src <project>/tb

void kernel(float A[32][32], float B[32][32], float C[32][32]) {
    #pragma HLS INTERFACE m_axi port=A bundle=gmem
    #pragma HLS INTERFACE m_axi port=B bundle=gmem
    #pragma HLS INTERFACE m_axi port=C bundle=gmem

    for (int i = 0; i < 32; i++) {
        for (int j = 0; j < 32; j++) {
            #pragma HLS PIPELINE II=1
            float sum = 0;
            for (int k = 0; k < 32; k++) {
                sum += A[i][k] * B[k][j];
            }
            C[i][j] = sum;
        }
    }
}

#pragma HLS ARRAY_PARTITION variable=input_data type=cyclic factor=4 dim=1
#pragma HLS ARRAY_PARTITION variable=weights type=complete dim=1

void top(hls::stream<int> &in, hls::stream<int> &out) {
    #pragma HLS DATAFLOW
    hls::stream<int> fifo1, fifo2;
    #pragma HLS STREAM variable=fifo1 depth=16
    #pragma HLS STREAM variable=fifo2 depth=16

    read_image(in, fifo1);
    process_image(fifo1, fifo2);
    write_image(fifo2, out);
}

#include "hls_stream.h"

void axis_process(hls::stream<ap_int<32>> &in, hls::stream<ap_int<32>> &out) {
    #pragma HLS INTERFACE axis port=in
    #pragma HLS INTERFACE axis port=out
    #pragma HLS PIPELINE II=1

    ap_int<32> data = in.read();
    // Data processing
    out.write(data);
}

#include "ap_fixed.h"
// ap_fixed<total_width, integer_bits, quantization_mode, overflow_mode>
typedef ap_fixed<16, 8, AP_RND, AP_SAT> fixed_t;
fixed_t value = 1.5f; // Automatic quantization

© Shinei-Nouzen-Arch, GPL-2.0. Rendered from Markdown: HTML in the file is shown as text, images as links, and headings moved down two levels. Raw file

Files

SKILL.md and 1,075 other files in vitis-hls-synthesis of Shinei-Nouzen-Arch/FPGA-Agent.

• SKILL.md
• REFERENCE.md
• agents/openai.yaml
• examples/Design_Tutorials/02-Beamformer/Makefile
• examples/Design_Tutorials/02-Beamformer/README.md
• examples/Design_Tutorials/02-Beamformer/description.json
• examples/Design_Tutorials/02-Beamformer/images/Beamformer.PNG
• examples/Design_Tutorials/02-Beamformer/images/Development_Time.PNG
• examples/Design_Tutorials/02-Beamformer/images/HLS_MATLAB_flow.png
• examples/Design_Tutorials/02-Beamformer/images/Results_Versal.PNG
• examples/Design_Tutorials/02-Beamformer/images/Results_Zynq.PNG
• examples/Design_Tutorials/02-Beamformer/project.cfg
• examples/Design_Tutorials/02-Beamformer/project.py
• examples/Design_Tutorials/02-Beamformer/reference_files/mgs_qrd_wbs.cpp
• examples/Design_Tutorials/02-Beamformer/reference_files/mgs_qrd_wbs.h
• … and 1,061 more

Open the folder on GitHubat commit b60a52e