By hdl-tools

Microarchitecture exploration, PPA estimation, risk assessment, and architecture sign-off for digital chip design.

hdl-tools/digital-chip-design-agents

Compiler toolchain development for custom processor ISAs — LLVM/GCC backend, assembler, linker scripts, runtime libraries, and regression validation.

hdl-tools/digital-chip-design-agents

Design for Test — scan architecture planning, scan insertion, ATPG pattern generation, MBIST for embedded memories, and JTAG boundary scan.

hdl-tools/digital-chip-design-agents

Embedded firmware and device drivers — BSP development, peripheral driver implementation (UART, SPI, I2C, GPIO, DMA, Timer), RTOS integration (FreeRTOS, Zephyr), and system validation.

hdl-tools/digital-chip-design-agents

Formal property verification (FPV) and logical equivalence checking (LEC).

hdl-tools/digital-chip-design-agents

FPGA prototyping — ASIC-to-FPGA RTL adaptation, multi-FPGA partitioning, synthesis and timing closure on FPGA, hardware bring-up, and software validation on the prototype.

hdl-tools/digital-chip-design-agents

UVM-based functional verification — testbench architecture, test planning, directed and constrained-random stimulus, functional and code coverage closure, formal assist, and regression sign-off.

hdl-tools/digital-chip-design-agents

High-Level Synthesis — C/C++ algorithm analysis, HLS directive optimisation, synthesis execution, and co-simulation verification.

hdl-tools/digital-chip-design-agents

Logic synthesis from RTL to gate-level netlist — SDC constraint validation, compile and optimisation strategy, netlist quality check, and LEC equivalence verification.

hdl-tools/digital-chip-design-agents

Full physical design flow — floorplan, placement, clock tree synthesis, routing, timing optimisation, power optimisation, area optimisation, and tape-out sign-off.

hdl-tools/digital-chip-design-agents

SoC IP integration — IP procurement and qualification, IP configuration, bus fabric setup, top-level RTL integration, and chip-level simulation.

hdl-tools/digital-chip-design-agents

Static timing analysis — multi-corner constraint validation, setup and hold analysis, timing exception review, and ECO guidance for closure.

hdl-tools/digital-chip-design-agents

EDA tool detection, wrapper deployment, and MCP configuration for digital chip design environments.

hdl-tools/digital-chip-design-agents

Embedded memory IP design — SRAM/register-file/ROM requirements capture, memory compiler and macro selection, array architecture (banking, ports, ECC wrapper), redundancy and repair allocation, view…

hdl-tools/digital-chip-design-agents

Cross-domain loop orchestration for the chip design pipeline.

hdl-tools/digital-chip-design-agents

SystemVerilog RTL design — module planning, coding standards enforcement, lint checking, CDC/RDC analysis, and synthesis readiness verification.

hdl-tools/digital-chip-design-agents

Distil accumulated experience records (experiences.jsonl) into updated domain knowledge summaries (knowledge.md) for any chip-design domain.

hdl-tools/digital-chip-design-agents