Sta

Skill: Static Timing Analysis (STA)

Invocation

When this skill is loaded and a user presents a timing analysis task, do not execute stages directly. Immediately spawn the digital-chip-design-agents:sta-orchestrator agent and pass the full user request and any available context to it. The orchestrator enforces the stage sequence, loop-back rules, and sign-off criteria defined below.

Use the domain rules in this file only when the orchestrator reads this skill mid-flow for stage-specific guidance, or when the user asks a targeted reference question rather than requesting a full flow execution.

Pre-run Context

Before executing or advising on any stage, read the following files if they exist:

1. memory/sta/knowledge.md — known failure patterns, successful tool flags, PDK/tool quirks. Incorporate its guidance into every stage decision. If absent, proceed without it.
2. memory/sta/run_state.md — current run identity (run_id, design_name, tool, last_stage). Use this to resume correctly after interruption. If absent, a new run is starting; the orchestrator will create this file before the first stage.

This pre-run read applies whether this skill is loaded by a user or called by the orchestrator mid-flow. It ensures the fix database is consulted before any diagnosis step.

Purpose

Multi-corner, multi-mode timing analysis, exception review, ECO-guided closure, and timing sign-off. WNS ≥ 0 and TNS = 0 at all corners required for tape-out.

Supported EDA Tools

Open-Source

• OpenSTA (sta) — standalone open-source STA; runs tcl scripts in batch mode (see sequential flow note below)
• OpenROAD STA subsystem (openroad -no_init) — STA within the OpenROAD PD flow; runs sequentially via tcl script

Proprietary

• Synopsys PrimeTime (pt_shell, dialect synopsys) — gold-standard multi-corner STA and power analysis
• Cadence Tempus (tempus, dialect cadence) — concurrent multi-mode multi-corner STA with ECO guidance

Sequential Flow Log Review (OpenSTA / OpenROAD STA)

OpenSTA (sta) and the OpenROAD STA subsystem (openroad -no_init) execute tcl script commands sequentially. When run in batch mode the agent must parse the output log to extract timing results — there is no interactive prompt to query mid-run.

Key log patterns to parse after run completion:

• report_timing output → extract WNS (worst negative slack) and critical path
• report_tns output → extract TNS (total negative slack) per corner
• report_clock_skew output → global skew and insertion delay per clock group
• check_timing → missing constraints, unconstrained endpoints, loops

Batch invocation:

opensta -no_splash -exit timing_check.tcl > sta.log 2>&1
# or via OpenROAD:
openroad -no_init -exit sta.tcl > sta.log 2>&1

Parse sta.log after completion. Apply loop-back rules (ECO guidance stage) if setup/hold violations are found.

Stage: constraint_validation

Validation Checks

1. All clocks defined with correct period and waveform
2. All generated clocks: correct source and division/multiplication
3. No unconstrained paths: verify with report_timing -unconstrained
4. CDCs: correct false_path or max_delay applied
5. Multicycle paths: both –setup N and –hold 1 specified
6. Input/output delays: match system-level timing budget
7. Timing exceptions: not overly broad (masking real violations)
8. Propagated vs ideal clocks: correct mode (ideal pre-CTS, propagated post-CTS)

Common Constraint Errors

QoR Metrics to Evaluate

• 0 unconstrained paths
• 0 clock definition errors
• All exceptions reviewed and documented

Output Required

• Constraint QA report
• Clock summary (all clocks, sources, periods)
• Exception list with justifications

Stage: multi_corner_analysis

Required Corner Matrix

Corners are driven by design_state.constraints.pvt_corners[]. The table below shows the default corners used when pvt_corners is absent or contains no entries with non-null V/T:

When pvt_corners is populated, use every entry with "checks": ["setup"] for setup and every entry with "checks": ["hold"] for hold; the defaults above are the fallback.

POCV/AOCV Application

1. AOCV: apply depth and location-based derating (pre-POCV designs)
2. POCV: apply parametric variation (sigma-based, per foundry agreement)
3. Clock uncertainty: pre-CTS ideal values → post-CTS propagated

Path Analysis Priority

1. WNS path per corner (most critical single path)
2. TNS contribution (how many paths fail and by how much)
3. CDC paths with max_delay constraints
4. At-speed paths: launch/capture pair STA

QoR Metrics — Sign-off Targets

Output Required

• Timing report per corner (setup and hold)
• WNS/TNS summary table across all corners
• Top 100 violating paths

Stage: path_analysis

Domain Rules

1. Group failing paths by root cause: long wire, weak driver, logic depth, high-Vt
2. Separate setup violations from hold violations — different fix strategies
3. At-speed violations: check launch/capture pair timing explicitly
4. False paths: verify every exception is still valid after PD changes
5. Reconvergent fanout: flag paths with reconvergence for careful ECO planning

Output Required

• Failing path analysis (root cause per path group)
• Paths requiring ECO vs paths requiring SDC correction

Stage: exception_review