Logic Synthesis

Skill: Logic Synthesis

Invocation

• If invoked by a user presenting a synthesis task: immediately spawn the digital-chip-design-agents:synthesis-orchestrator agent and pass the full user request and any available context. Do not execute stages directly.
• If invoked by the synthesis-orchestrator mid-flow: do not spawn a new agent. Treat this file as read-only — return the requested stage rules, sign-off criteria, or loop-back guidance to the calling orchestrator.

Spawning the orchestrator from within an active orchestrator run causes recursive delegation and must never happen.

Pre-run Context

Before executing or advising on any stage, read the following files if they exist:

1. memory/synthesis/knowledge.md — known failure patterns, successful tool flags, PDK/tool quirks. Incorporate its guidance into every stage decision. If absent, proceed without it.
2. memory/synthesis/run_state.md — current run identity (run_id, design_name, tool, last_stage). Use this to resume correctly after interruption. If absent, a new run is starting; the orchestrator will create this file before the first stage.

This pre-run read applies whether this skill is loaded by a user or called by the orchestrator mid-flow. It ensures the fix database is consulted before any diagnosis step.

Purpose

Produce a timing-clean, area-efficient, LEC-verified gate-level netlist from RTL. Covers constraint setup, synthesis compilation strategy, and quality checks before PD handoff.

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Supported EDA Tools

Open-Source

• Yosys (yosys) — open-source synthesis suite; runs as a sequential pass pipeline (see sequential flow note below)
• Surelog (surelog) — SystemVerilog front-end for Yosys
• ABC — logic optimisation and technology mapping (invoked automatically by Yosys)

Proprietary

• Synopsys Design Compiler (dc_shell, dialect synopsys) — industry-standard logic synthesis
• Cadence Genus (genus, dialect cadence) — RTL-to-netlist with concurrent optimisation
• Synopsys Fusion Compiler (fc_shell, dialect synopsys) — combined synthesis and physical guidance

Sequential Flow Log Review (Yosys)

Yosys runs its synthesis script (yosys -c synth.ys or yosys -p "synth_*") as a sequential pass pipeline. Each pass (read_verilog → synth → opt → techmap → abc → write_verilog) executes in order; errors or warnings in early passes propagate forward.

After a Yosys run the agent must:

1. Read the Yosys log (stdout or redirected yosys.log) for:
   • Warning: / Error: lines per pass
   • Final statistics block: number of cells, wires, and logic depth
   • Unmapped cells (search for $-prefixed cell names in the output netlist)
2. Verify that the output netlist (synth_netlist.v) exists and is non-empty
3. Parse report_area / report_timing output if ABC timing mode (abc -constr) was used

When used inside OpenROAD Flow Scripts (ORFS) or LibreLane, the Yosys log appears at: logs/<platform>/<design>/1_1_yosys.log

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Stage: constraint_setup

Domain Rules

1. create_clock: all primary clocks with period, waveform, source pin, name
2. create_generated_clock: all derived/divided clocks with correct source
3. set_clock_uncertainty: setup = skew + jitter — use design_state.constraints.timing.clk_uncertainty_ps if set; otherwise 200–500 ps pre-CTS (default: see constraints.timing.clk_uncertainty_ps, schema default null → use 200–500 ps rule-of-thumb)
4. set_input_delay / set_output_delay: all primary IOs constrained
5. set_false_path: multi-clock crossings, test modes, async resets
6. set_multicycle_path: both setup (-setup N) and hold (-hold 1) must be set
7. set_dont_touch: IPs, memory macros, hand-crafted cells
8. set_max_fanout: from design_state.constraints.timing.fanout_max (default: 32)
9. set_max_transition: per technology DRC rule
10. Operating conditions: explicitly set (never rely on tool defaults)

Common SDC Mistakes

QoR Metrics to Evaluate

• All clocks defined (verify with report_clocks)
• All IOs constrained (verify with report_port -verbose)
• No unconstrained paths (report_timing -unconstrained)

Output Required

• Validated SDC file
• Clock summary
• Constraint QA report

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Stage: compile_explore

Domain Rules

1. Run at worst-case timing corner (SS, low voltage, high temperature)
2. Compile explore: faster run to find best logic structure
3. Try multiple architectures: retiming on/off, datapath options
4. Identify critical paths for human review before final compile
5. Check area estimate vs microarch estimate

Optimisation Strategy by Priority

Output Required

• Exploration report (timing, area, power summary)
• Critical path list for architect review
• Recommended compile strategy for final compile

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Stage: compile_final

Domain Rules

1. Run multi-scenario if available (setup + hold simultaneously)
2. Enable clock gating synthesis for sequential power reduction
3. Preserve hierarchy for blocks with existing placement intent
4. Ungroup small modules for better cross-boundary optimisation
5. Review critical paths manually — restructure RTL if path cannot close
6. Run incremental compile after initial compile to address remaining violations