Compiler Toolchain

Skill: Compiler Toolchain Development

Invocation

When this skill is loaded and a user presents a compiler or ISA task, do not execute stages directly. Immediately spawn the digital-chip-design-agents:compiler-orchestrator agent and pass the full user request and any available context to it. The orchestrator enforces the stage sequence, loop-back rules, and sign-off criteria defined below.

Use the domain rules in this file only when the orchestrator reads this skill mid-flow for stage-specific guidance, or when the user asks a targeted reference question rather than requesting a full flow execution.

Pre-run Context

Before executing or advising on any stage, read the following files if they exist:

1. memory/compiler/knowledge.md — known failure patterns, successful tool flags, PDK/tool quirks. Incorporate its guidance into every stage decision. If absent, proceed without it.
2. memory/compiler/run_state.md — current run identity (run_id, design_name, tool, last_stage). Use this to resume correctly after interruption. If absent, a new run is starting; the orchestrator will create this file before the first stage.

This pre-run read applies whether this skill is loaded by a user or called by the orchestrator mid-flow. It ensures the fix database is consulted before any diagnosis step.

Purpose

Build and validate a complete compiler toolchain (LLVM or GCC based) for a custom processor ISA. Bridges hardware and software — without a working toolchain no software can run on the designed chip.

Supported EDA Tools

Open-Source

• LLVM/Clang (clang, llc, llvm-mc, llvm-objdump) — primary toolchain for new ISA backends
• GCC and GNU Binutils (gcc, as, ld, objdump) — alternative backend; well-tested for RISC-V extensions
• QEMU (qemu-system-*) — instruction-accurate ISA emulation for toolchain validation without hardware

Proprietary

• Green Hills MULTI (dialect greenhills) — safety-critical compiler and debugger IDE
• IAR Embedded Workbench (dialect iar) — certified compiler for ARM/RISC-V
• Arm Compiler 6 (armcc, dialect arm) — LLVM-based compiler for Arm targets

Stage: isa_analysis

ISA Feature → Toolchain Component Mapping

ABI Requirements (define before any backend code)

1. Argument passing: which registers, stack spill rules
2. Return value registers
3. Callee-saved vs caller-saved register classification
4. Stack alignment (8 or 16 byte)
5. Data type sizes and alignments
6. Struct layout (padding, packing rules)
7. Thread-local storage model (if RTOS target)

Output Required

• ISA-to-toolchain mapping table
• ABI specification document
• List of LLVM/GCC backend files to create/modify
• Target triple: <arch>-<vendor>-<os>

Stage: backend_dev

LLVM Backend — Implement in This Order

1. RegisterInfo.td: register classes, aliases, reserved registers
2. InstrInfo.td: all instruction definitions with encoding
3. CallingConv.td: argument and return value register rules
4. SchedModel.td: latency and throughput per instruction class
5. TargetMachine.cpp: entry point, subtarget selection
6. ISelDAGToDAG.cpp: selection DAG → machine instruction lowering
7. FrameLowering.cpp: stack frame, prologue/epilogue
8. AsmPrinter.cpp: assembly text emission

Testing per Component

• TableGen: llvm-tblgen compiles .td without errors
• Codegen: llc compiles C snippets; verify .s output manually
• MC layer: llvm-mc --show-encoding verifies instruction encoding

QoR Metrics to Evaluate

• All ISA instruction classes: lowerable from LLVM IR
• Calling convention: function call round-trip test passes
• No illegal instructions in generated assembly
• Basic integer test program: compiles, links, executes on ISS

Common Issues & Fixes

Output Required

• Complete LLVM backend source tree
• Regression test files (llc lit tests)
• Build instructions (CMake)

Stage: assembler_dev

Domain Rules

1. LLVM MC layer provides assembler via .td instruction definitions
2. For every instruction: encode-decode round-trip test
3. Define all ELF relocation types: R_<ARCH>_*
4. Directives: .section, .global, .type, .size, .align all working
5. DWARF: verify .debug_info emitted for a C function (needed for GDB)
6. Branch offsets: verify PC-relative encoding for forward and backward branches
7. Immediate ranges: verify truncation and sign-extension at instruction boundaries

QoR Metrics to Evaluate

• All instructions: encode-decode round-trip passes
• All relocation types: defined and tested
• ELF output: readable by readelf -a
• DWARF: basic debug info emitted

Output Required

• Assembler integrated in LLVM MC layer
• Encoding test suite (one test per instruction format)
• Relocation definition table

Stage: linker_config

Linker Script Template

MEMORY {
  FLASH (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
  RAM   (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
}
ENTRY(_start)
SECTIONS {
  .text   : { *(.text.reset) *(.text*) *(.rodata*) } > FLASH
  .data   : { *(.data*) }  > RAM AT > FLASH
  .bss    : { *(.bss*) *(COMMON); PROVIDE(__bss_end = .); } > RAM
  .stack  : { . = ALIGN(16); PROVIDE(__stack_top = .); . += STACK_SIZE; } > RAM
}

Domain Rules

1. Memory regions must match chip memory map exactly
2. Startup code (crt0.S): copy .data LMA→VMA; zero .bss; call main()
3. Stack defined via linker symbol __stack_top; size configurable at link time
4. All relocation types from assembler stage must be handled
5. Verify: bare-metal binary links, loads, executes from reset vector