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Agent skill

Fpga Emulation

by hdl-tools in hdl-tools/digital-chip-design-agents

FPGA prototyping — ASIC-to-FPGA RTL adaptation, multi-FPGA partitioning, synthesis and timing closure on FPGA, hardware bring-up, and software validation on the prototype.

MITAuto-check: notesDevelopment

Install Fpga Emulation

skills CLI
$ npx skills add hdl-tools/digital-chip-design-agents --skill fpga-emulation -a claude-code

Project install by default; add -g for ~/.claude/skills/.

GitHub CLI
$ gh skill install hdl-tools/digital-chip-design-agents fpga-emulation --agent claude-code

Project scope by default; add --scope user for a personal install. Needs GitHub CLI 2.90.0 or later (public preview).

Manual copy
$ git clone --depth 1 https://github.com/hdl-tools/digital-chip-design-agents.git skills-src && mkdir -p .claude/skills && cp -r skills-src/plugins/fpga/skills/fpga-emulation .claude/skills/fpga-emulation && rm -rf skills-src

Use ~/.claude/skills/ instead of .claude/skills for a personal install. The folder must contain SKILL.md.

Claude Code skills documentation · loads skills from .claude/skills/

Facts

Skill name
fpga-emulation
GitHub stars
213
Token cost
~3.4k tokens
SKILL.md length
1,596 words
Files
1
Skills in repo
17
Repo updated
First seen
Licence
MIT

At a glance

FPGA prototyping — ASIC-to-FPGA RTL adaptation, multi-FPGA partitioning, synthesis and timing closure on FPGA, hardware bring-up, and software validation on the prototype.

  • Works in 2 steps: memory/fpga/knowledge.md — known failure… → memory/fpga/run_state.md — current run…
  • Porting an ASIC design to Xilinx
  • SKILL.md covers Invocation, Pre-run Context, Purpose and Supported EDA Tools, plus 5 more sections
  • Instructions only: no scripts, shell commands, URLs or credentials in SKILL.md

What it does

Fpga Emulation is an agent skill from hdl-tools/digital-chip-design-agents. FPGA prototyping — ASIC-to-FPGA RTL adaptation, multi-FPGA partitioning, synthesis and timing closure on FPGA, hardware bring-up, and software validation on the prototype. Use when porting an ASIC design to Xilinx or Intel FPGA for pre-silicon software development and hardware validation.

Its SKILL.md is about 3.4k tokens, which your agent loads only when the skill is triggered. It is a single SKILL.md file with no bundled scripts.

It sits in Development, covering Prototyping. The repository describes itself as: Digital HDL Design Full-stack Agents. The licence is MIT.

When your agent uses it

  • Porting an ASIC design to Xilinx
  • Intel FPGA for pre-silicon software development and hardware validation

Example prompts

  • “/fpga-emulation”

Requirements

  • Pre-approved tools (allowed-tools): Read, Write, Bash

Workflow steps

2 steps, taken from the first numbered list in SKILL.md.

  1. memory/fpga/knowledge.md — known failure patterns, successful tool flags, PDK/tool quirks.
  2. memory/fpga/run_state.md — current run identity (run_id, design_name, tool,

What it can do on your machine

Read from SKILL.md and the folder at commit 38736b1. It shows what the files ask for, not the result of running them.

  • Tool permissions

    Pre-approves these tools, so the agent can use them without asking each time:

    • Read
    • Write
    • Bash

    From allowed-tools in the SKILL.md frontmatter.

  • Runs code

    No scripts in the folder and no shell commands in SKILL.md (its code samples are markdown).

    From the folder's file list and the shell code blocks in SKILL.md.

  • Network

    No URLs in SKILL.md.

    From URLs in SKILL.md, links to its own repository left out.

  • Credentials

    Names no API keys, tokens, secrets or passwords.

    From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.

Context cost

Fpga Emulation loads about 3.4k tokens when it runs. Until then it costs about 76 tokens; SKILL.md has 1,596 words of instructions outside code blocks.

Always · name and description, kept in context so the agent knows when to use it
~76
When it runs · the whole SKILL.md, loaded when a task matches
~3.4k

Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.

Safety

Auto-check: notes

The automated check noted patterns worth knowing about, such as sudo or a known installer.

  • NotePre-approves every shell command (allowed-tools: Bash)SKILL.md
    allowed-tools: Read, Write, Bash

Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.

SKILL.md

The full file from hdl-tools/digital-chip-design-agents at commit 38736b1, republished under its MIT licence (© hdl-tools). 1,596 words, ~3,375 tokens.

Download SKILL.mdSave it as .claude/skills/fpga-emulation/SKILL.md (or your agent's skills folder).
name
fpga-emulation
description
FPGA prototyping — ASIC-to-FPGA RTL adaptation, multi-FPGA partitioning, synthesis and timing closure on FPGA, hardware bring-up, and software validation on the prototype. Use when porting an ASIC design to Xilinx or Intel FPGA for pre-silicon software development and hardware validation.
allowed-tools
Read, Write, Bash
version
1.0.0
author
chuanseng-ng
license
MIT

Skill: FPGA Emulation & Prototyping

Invocation

  • If invoked by a user presenting an FPGA prototyping task: immediately spawn the digital-chip-design-agents:fpga-orchestrator agent and pass the full user request and any available context. Do not execute stages directly.
  • If invoked by the fpga-orchestrator mid-flow: do not spawn a new agent. Treat this file as read-only — return the requested stage rules, sign-off criteria, or loop-back guidance to the calling orchestrator.

Spawning the orchestrator from within an active orchestrator run causes recursive delegation and must never happen.

Pre-run Context

Before executing or advising on any stage, read the following files if they exist:

  1. memory/fpga/knowledge.md — known failure patterns, successful tool flags, PDK/tool quirks. Incorporate its guidance into every stage decision. If absent, proceed without it.
  2. memory/fpga/run_state.md — current run identity (run_id, design_name, tool, last_stage). Use this to resume correctly after interruption. If absent, a new run is starting; the orchestrator will create this file before the first stage.

This pre-run read applies whether this skill is loaded by a user or called by the orchestrator mid-flow. It ensures the fix database is consulted before any diagnosis step.

Purpose

Port an ASIC design to an FPGA prototype platform for pre-silicon hardware/ software co-development. The FPGA prototype is not cycle-accurate but provides functional and architectural validation months before silicon.

Supported EDA Tools

Open-Source
  • Yosys (yosys) — open-source synthesis for Xilinx/Intel/Lattice FPGA targets
  • nextpnr (nextpnr-xilinx, nextpnr-ice40, nextpnr-ecp5) — place-and-route for open-source flows
  • OpenFPGALoader (openFPGALoader) — universal FPGA programmer
  • Project IceStorm — iCE40 FPGA toolchain (icepack, iceprog, icetime)
  • Project X-Ray — Xilinx 7-series bitstream documentation
Proprietary
  • Xilinx Vivado (vivado, dialect xilinx) — synthesis, implementation, and bitstream generation for AMD/Xilinx
  • Intel Quartus (quartus_sh, dialect intel) — synthesis and programming for Intel/Altera FPGAs
  • Microchip Libero (libero, dialect microchip) — synthesis and programming for PolarFire/SmartFusion FPGAs
  • Synopsys Synplify (dialect synopsys) — FPGA synthesis front-end targeting multiple device families

Stage: rtl_adaptation

ASIC → FPGA Substitutions
ASIC ElementFPGA Replacement
SRAM macrosBRAM/URAM (Xilinx) or M20K (Intel)
Analog PLLsMMCM (Xilinx) or ALTPLL (Intel)
IO pad cellsFPGA IOB + IOBUF primitives
Analog/mixed-signalStub model or remove
DFT scan logicRemove — not needed on prototype
Power management cellsRemove — FPGA handles internally
Memory Replacement Rules
  1. Match port configuration (single-port vs dual-port)
  2. BRAM has 1-cycle read latency — verify RTL handles this
  3. Memories > available BRAM: use external DDR via MIG/HBM controller
  4. Use XPM_MEMORY (Xilinx) or equivalent portable macros
Clock Replacement Rules
  1. Replace ASIC PLL with MMCM (Xilinx) or ALTPLL (Intel)
  2. Scale all clocks to FPGA prototype frequency (typically 50–100 MHz from ≥ 1 GHz ASIC)
  3. Maintain same ratio between clock domains
  4. Use BUFG for all global clocks — never route clocks on data fabric
Adapted RTL Rules
  1. Adapted RTL meets the rtl-design skill's lint_check ERROR rules (latches, multiple drivers, undriven outputs). Re-lint after every edit, including edits made on a loop-back from fpga_synthesis, bring_up or sw_validation
  2. Match the conventions of the ASIC file being adapted; do not restyle RTL you are only retargeting
  3. initial blocks are permitted for FPGA memory and register initialisation, but only in FPGA-only files or under an FPGA-specific `ifdef — the ASIC source must stay free of them
  4. Vendor primitives and macros (XPM_MEMORY, MMCM, BUFG, IOBUF) are unknown modules to an open-source linter. Lint with unknown modules ignored and treat undriven-net findings on their outputs as stub artefacts, not errors
QoR Metrics to Evaluate
  • No ASIC-specific primitives remain in adapted RTL
  • All memories mapped to BRAM or external DDR
  • Adapted RTL: lint clean, 0 errors
  • Functional sim: adapted RTL produces same outputs as ASIC RTL
Output Required
  • Adapted RTL file set
  • Substitution log (what was replaced and why)
  • BRAM and MMCM resource estimate

Stage: partitioning

Domain Rules
  1. Target utilisation per FPGA: < design_state.constraints.fpga.lut_util_pct_max% LUT (default: 70%) — leave room for ILA debug cores
  2. Minimise inter-FPGA signal count — each signal uses a physical connector pin
  3. Never cut timing-critical paths at partition boundaries
  4. Keep complete clock domains within a single FPGA wherever possible
  5. Inter-FPGA: Aurora or GTH SERDES for high-speed; GPIO for slow control
QoR Metrics to Evaluate
  • Per-FPGA: LUT < design_state.constraints.fpga.lut_util_pct_max% (default: 70%), BRAM < design_state.constraints.fpga.bram_util_pct_max% (default: 80%), DSP < design_state.constraints.fpga.dsp_util_pct_max% (default: 80%)
  • Inter-FPGA signal count: within connector pin budget
  • No clock domain split without explicit bridge
Output Required
  • Partition plan (block → FPGA mapping)
  • Inter-FPGA signal list
  • Physical connector pin assignment

Stage: fpga_synthesis

Domain Rules
  1. Full Vivado (Xilinx) or Quartus (Intel) flow: synth → opt → place → route → phys_opt → bitstream
  2. Timing target: WNS ≥ design_state.constraints.timing.wns_ns_target (default: 0) at prototype frequency
  3. If WNS < 0: reduce frequency first; add pipeline registers second
  4. Utilisation targets: LUT < design_state.constraints.fpga.lut_util_pct_max% (default: 70%), BRAM < design_state.constraints.fpga.bram_util_pct_max% (default: 80%), DSP < design_state.constraints.fpga.dsp_util_pct_max% (default: 80%)
Debug Infrastructure (add before bitstream)
  • ILA: up to 64 probes per core; trigger on errors or key FSM states
  • VIO: drive and sample control/status signals from PC
  • JTAG-to-AXI: register access from PC without re-synthesising
Timing Closure Techniques
TechniqueWhen to Apply
Reduce clock frequencyFirst option — accept slower prototype
Add pipeline registersWhen path identifiable and latency increase acceptable
Pblock constraintsCo-locate logic near BRAMs/DSPs
BUFG on high-fanout netBreak long high-fanout routes
phys_opt –directive AggressiveExploreLast resort
QoR Metrics to Evaluate
  • WNS ≥ design_state.constraints.timing.wns_ns_target (default: 0) at prototype frequency
  • LUT < design_state.constraints.fpga.lut_util_pct_max% (default: 70%), BRAM < design_state.constraints.fpga.bram_util_pct_max% (default: 80%), DSP < design_state.constraints.fpga.dsp_util_pct_max% (default: 80%)
  • Bitstream: no critical DRC errors
  • ILA: configured on key debug signals
Output Required
  • Bitstream (.bit or .sof)
  • Timing summary report
  • Utilisation report
  • ILA probe definition file

Stage: bring_up

Bring-up Sequence (follow in order)
  1. Power-on: measure power rails; current within spec
  2. FPGA configuration: load bitstream via JTAG or SPI flash
  3. Clock verification: oscilloscope or ILA — verify frequency and stability
  4. Reset: toggle reset; verify all status bits de-assert
  5. Register access via JTAG-to-AXI: read chip-ID register — first functional test
  6. Memory test: write and read-back BRAM and external DDR
  7. UART console: CPU outputs boot messages — verify on serial terminal
  8. Minimal firmware: bare-metal binary executes and prints PASS
Show full SKILL.md (624 more words)Show less
Common Failures
SymptomLikely CauseFix
MMCM lock never setsPLL input freq out of rangeRecheck MMCM config
CPU never outputs UARTWrong reset vector or memory mapCheck linker script
Register reads 0x00000000Base address wrong in SWCompare memory_map.h vs HW
Register reads 0xDEADBEEFOut-of-range access → DECERRFix address in driver
Intermittent data corruptionCDC issue in adapted RTLReview clock crossings
QoR Metrics to Evaluate
  • All clocks: correct frequency (measured)
  • CPU: reaches UART prompt
  • All peripheral registers: readable/writable via JTAG
  • DDR memory test: passes (if present)
Output Required
  • Bring-up test results log
  • ILA captures for any failures
  • Known issues list for SW team

Stage: sw_validation

Domain Rules
  1. Run embedded-firmware skill validation suite on FPGA prototype
  2. Scale all timeouts by FPGA-to-ASIC frequency ratio (e.g., 20× for 50 MHz vs 1 GHz)
  3. Record all performance measurements at FPGA frequency; note scale factor
Hardware Bug vs Software Bug Triage
  1. Reproducible deterministically? → likely HW bug
  2. Same failure in RTL simulation? → RTL bug (fix RTL, not just firmware)
  3. Different from RTL sim? → FPGA adaptation issue
  4. Intermittent? → CDC or timing margin issue
Validation Tiers on Prototype
TestPass Criteria
BSPAll peripherals accessible
Driver unit100% per driver
SystemCorrect output vs golden
Long-run (4 hr)0 lockups, 0 unexpected resets
QoR Metrics to Evaluate
  • All driver tests: PASS on prototype
  • Application: correct output vs golden reference
  • No lockups or unexpected resets in stress test
  • Performance baseline: recorded at prototype frequency
Output Required
  • SW validation report
  • Performance baseline (labelled as prototype-frequency values)
  • Bug list (HW vs SW classification)
  • Performance projection to silicon frequency

Stage: proto_signoff

Sign-off Checklist
  • All clocks verified at correct frequency
  • CPU boots and reaches application code
  • All peripheral registers accessible
  • All driver tests pass on prototype
  • Application produces correct output
  • 4-hour stress: clean
  • All HW bugs filed to RTL team with ILA captures
  • Performance baseline documented
Output Required
  • Prototype sign-off report
  • Bug report for RTL team (HW bugs with ILA evidence)
  • Performance baseline document
  • Prototype user guide for SW development team

Constraint Validation

See plugins/meta/skills/pipeline-orchestration/SKILL.md §Constraints Schema for the authoritative schema and stage-entry validation rule.

Required at entry (rtl_adaptation) — hard-fail if missing:

  • constraints.clock.clk_mhz — ASIC target clock frequency; used to compute FPGA prototype frequency scale-down ratio

Optional (schema defaults apply when absent):

  • constraints.timing.wns_ns_target (default: 0) — WNS closure threshold at prototype frequency
  • constraints.fpga.lut_util_pct_max (default: 70) — per-FPGA LUT utilisation ceiling %
  • constraints.fpga.bram_util_pct_max (default: 80) — per-FPGA BRAM utilisation ceiling %
  • constraints.fpga.dsp_util_pct_max (default: 80) — per-FPGA DSP utilisation ceiling %

Memory

Write on stage completion

After each stage completes (regardless of whether an orchestrator session is active), write or overwrite one JSON record in memory/fpga/experiences.jsonl keyed by run_id. This ensures data is persisted even if the flow is interrupted or called without full orchestrator context. Use the experience record schema in memory/README.md, with key_metrics fields lut_count, fmax_mhz, timing_met.

Use run_id = fpga_<YYYYMMDD>_<HHMMSS>_<6-char-random> where the 6-character suffix is a lowercase hexadecimal string [0-9a-f] generated once at flow start using a secure or pseudorandom RNG and reused unchanged on every stage update for this run. signoff_achieved is a JSON boolean: set signoff_achieved: false until the final sign-off stage completes.

Run state (write before first stage, update after each stage)

Write memory/fpga/run_state.md as the first action before launching any tool:

markdown
run_id:        fpga_<YYYYMMDD>_<HHMMSS>_<6-char-random>
design_name:   <design>
tool:          <primary tool>
start_time:    <ISO-8601>
last_stage:    null
current_stage: <first stage name>

The 6-character random suffix must be lowercase hexadecimal [0-9a-f]. Update current_stage when a stage starts, and set last_stage to the completed stage name only after successful completion (then clear current_stage). This file lets wakeup-loop prompts and resumed sessions identify the correct run. Create the file and parent directories if they do not exist.

Optional: claude-mem index

If mcp__plugin_ecc_memory__add_observations is available in this session, emit each applied fix as an observation to entity chip-design-fpga-fixes after writing to experiences.jsonl. Skip silently if the tool is absent — JSONL is the canonical record.

© hdl-tools, MIT. Rendered from Markdown: HTML in the file is shown as text, images as links, and headings moved down two levels. Raw file

Files

Just SKILL.md in plugins/fpga/skills/fpga-emulation of hdl-tools/digital-chip-design-agents.

Open the folder on GitHubat commit 38736b1

Compare with similar skills

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Collaborating With CodexGuDaStudio/collaborating-with-codex1321 repos~712Automated safety check: PassMIT
Digikeyaklofas/kicad-happy1.4k1 repos~4.5kAutomated safety check: PassMIT
Collaborating With Geminihaoyu-haoyu/Multi-AI-Workflow109—~521Automated safety check: PassMIT

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Categories

Questions about Fpga Emulation

What does Fpga Emulation do?

FPGA prototyping — ASIC-to-FPGA RTL adaptation, multi-FPGA partitioning, synthesis and timing closure on FPGA, hardware bring-up, and software validation on the prototype. Fpga Emulation is an agent skill from hdl-tools/digital-chip-design-agents. FPGA prototyping — ASIC-to-FPGA RTL adaptation, multi-FPGA partitioning, synthesis and timing closure on FPGA, hardware bring-up, and software validation on the prototype.

When should I use Fpga Emulation?

Fpga Emulation fits situations like: porting an ASIC design to Xilinx; intel FPGA for pre-silicon software development and hardware validation.

How do I install Fpga Emulation in Claude Code?

Run `npx skills add hdl-tools/digital-chip-design-agents --skill fpga-emulation -a claude-code`. Or copy the skill folder (plugins/fpga/skills/fpga-emulation in hdl-tools/digital-chip-design-agents) into .claude/skills/fpga-emulation in your project. Claude Code loads it when a task matches its description.

How do I install Fpga Emulation in Codex?

Run `npx skills add hdl-tools/digital-chip-design-agents --skill fpga-emulation -a codex`. Or copy the skill folder (plugins/fpga/skills/fpga-emulation in hdl-tools/digital-chip-design-agents) into .agents/skills/fpga-emulation in your project. Codex loads it when a task matches its description.

Can I use Fpga Emulation in Cursor, Gemini CLI or GitHub Copilot?

Cursor, Gemini CLI, GitHub Copilot and OpenCode also load SKILL.md folders. With the skills CLI, run `npx skills add hdl-tools/digital-chip-design-agents --skill fpga-emulation -a cursor` (or -a gemini-cli, github-copilot or opencode for the others). To copy it by hand, put the folder in .cursor/skills/fpga-emulation, .gemini/skills/fpga-emulation, .github/skills/fpga-emulation and .opencode/skills/fpga-emulation in your project.

What does Fpga Emulation need to run?

SKILL.md names no scripts, command-line tools or credentials: Fpga Emulation is instructions for the agent only. Its frontmatter pre-approves these tools: Read, Write, Bash.

Does Fpga Emulation access the network?

SKILL.md contains no URLs. Any network use would come from the scripts or tools the agent runs. This is read from the text; nothing was executed.

Is Fpga Emulation safe to install?

Our automated static check of SKILL.md found notes only (pre-approves every shell command (allowed-tools: bash)), nothing it rates as a warning. It is not a guarantee. Review the folder before installing.

What licence does Fpga Emulation use?

Fpga Emulation is published under the MIT licence (declared in SKILL.md). It allows redistribution, so the full SKILL.md is shown on this page.

How many tokens does Fpga Emulation use?

About 3.4k tokens (SKILL.md is roughly 14k characters). Agents keep only the skill's name and description in context until a task matches; then they load SKILL.md in full.

What are the alternatives to Fpga Emulation?

Skills that share tags, products or a category with Fpga Emulation: Native Feel Cross Platform Desktop (yetone/native-feel-skill, 1.9k stars), Compound Engineering Prototype (EveryInc/compound-engineering-plugin, 25k stars), Collaborating With Codex (GuDaStudio/collaborating-with-codex, 132 stars) and Digikey (aklofas/kicad-happy, 1.4k stars). The comparison table on this page puts their stars, adoption, token cost, safety result and licence side by side.

Who maintains Fpga Emulation?

hdl-tools (a GitHub organization) maintains it in hdl-tools/digital-chip-design-agents, which has 213 GitHub stars. The repository holds 17 skills in this directory. The repository was last updated on October 3, 2026.

Source: hdl-tools/digital-chip-design-agents on GitHub. Facts on this page come from the repository at the commit we read; the author's words are quoted as theirs.