Soc Integration

Skill: SoC IP Integration

Invocation

When this skill is loaded and a user presents a SoC integration task, do not execute stages directly. Immediately spawn the digital-chip-design-agents:soc-integration-orchestrator agent and pass the full user request and any available context to it. The orchestrator enforces the stage sequence, loop-back rules, and sign-off criteria defined below.

Use the domain rules in this file only when the orchestrator reads this skill mid-flow for stage-specific guidance, or when the user asks a targeted reference question rather than requesting a full flow execution.

Pre-run Context

Before executing or advising on any stage, read the following files if they exist:

1. memory/soc/knowledge.md — known failure patterns, successful tool flags, PDK/tool quirks. Incorporate its guidance into every stage decision. If absent, proceed without it.
2. memory/soc/run_state.md — current run identity (run_id, design_name, tool, last_stage). Use this to resume correctly after interruption. If absent, a new run is starting; the orchestrator will create this file before the first stage.

This pre-run read applies whether this skill is loaded by a user or called by the orchestrator mid-flow. It ensures the fix database is consulted before any diagnosis step.

Purpose

Assemble a complete SoC from first-party RTL, licensed hard/soft IPs, and memory macros. Covers IP procurement, bus fabric configuration, top-level integration, and chip-level simulation sign-off.

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Supported EDA Tools

Open-Source

• Verilator (verilator) — fast simulation of the integrated top-level
• cocotb — Python co-simulation for bus-fabric and peripheral tests
• FuseSoC (fusesoc) — IP package manager and build system for SoC integration
• Edalize — EDA tool abstraction layer used with FuseSoC

Proprietary

• Synopsys VCS (vcs, dialect synopsys) — chip-level simulation with coverage
• Cadence Xcelium (xrun, dialect cadence) — multi-language chip-level simulation
• Siemens Questa (vsim, dialect siemens) — chip-level simulation and protocol checking

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Stage: ip_procurement

IP Qualification Checklist

• Deliverable format: RTL (.v/.sv), GDSII, or encrypted netlist?
• Technology node: certified for target process?
• Timing libraries: SS/TT/FF corners available?
• LEF/DEF: available for PD flow?
• Simulation models: behavioural/RTL for verification?
• UPF: power intent delivered?
• Databook: register map, timing diagrams, integration guide?
• DFT: scan-enabled? BIST available?
• Silicon proven: on which node?
• Support SLA: bug-fix and update commitment?

Hard IP vs Soft IP

Memory Macro Qualification

1. Verify compiler-generated views: .lib, .lef, .v (behavioural)
2. Check access time vs target frequency
3. Verify retention/power-down modes (for UPF power domains)
4. Confirm MBIST ports available

Output Required

• IP qualification report per IP
• IP deliverable checklist (all views received)
• IP risk register (gaps in deliverables)

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Stage: ip_configuration

Domain Rules

1. Configure each IP per its databook for target use case
2. Parameterise data widths, FIFO depths, feature enables
3. Verify configured timing meets design_state.constraints.clock.clk_mhz MHz target frequency at worst-case corner
4. Verify interface widths match bus fabric port requirements
5. Generate integration wrapper if IP port names differ from system conventions

Output Required

• Configured IP files and wrappers
• Timing verification report (configured corner)

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Stage: bus_fabric_setup

Bus Fabric Selection

Domain Rules

1. Non-overlapping address regions for all slaves
2. AXI width adapters for any width mismatches
3. Async bridges for all cross-clock-domain connections
4. QoS: assign traffic class for latency-sensitive masters
5. Error handling: out-of-range address → DECERR response defined

Memory Map Validation

• No address region overlaps
• All peripherals accessible from all required masters
• Reserved regions return DECERR
• No unintended address aliasing

QoR Metrics to Evaluate

• Address decode: complete, no gaps, no overlaps
• All IP blocks connected with correct port width
• CDC bridges in place for all clock crossings

Output Required

• Bus fabric configuration file
• Memory map document (final, versioned)
• Address decoder verification report

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Stage: top_integration

Domain Rules

1. Top module: wiring only — no logic at top level
2. All IPs instantiated once (no unintended duplicates)
3. All ports connected — lint check for unconnected active signals
4. Clock generation: PLL/mux module at or near top level
5. Reset generation: synchroniser per domain at top level
6. Tie cells: VDD/VSS tie-offs for all floating inputs
7. Scan chain: SI/SO routed through scan backbone
8. JTAG: TDI/TDO routed through JTAG chain
9. Instantiate every IP with named port connections — a positional connection silently mis-wires when an IP revision reorders its ports
10. Lint soc_top.sv in the context of the full SoC filelist, compiled as one unit. Linted alone, every IP is an unknown module and port-width mismatches go unchecked
11. An IP that is deliberately black-boxed (hard macro, analog block, encrypted IP) is a stub: undriven-net findings on its outputs are not connectivity errors. Record them as informational and name the stub, so a real unconnected port is not lost among them. A stub is benign only if you can name the macro or IP it stands for: an unknown module that resolves to first-party RTL in this repository is a missing filelist entry (rule 12)
12. An IP or module is not integrated until every tool's source list can see it. Simulation, lint, synthesis, PD and formal usually read separate lists, often Makefile variables, and a module missing from one is black-boxed by sv2v and yosys without an error while the chip-level regression, reading another list, stays green. Enumerate every list and confirm each new file is in each, or state why not; for .f lists run plugins/rtl-design/skills/rtl-design/check_design_inputs.py <filelist.f> --rtl-dir <rtl> --list <name>=<file> ...
13. Where a downstream flow converts the RTL before synthesis (sv2v, Surelog/UHDM), run the conversion on the SoC filelist and parse the output with the consuming tool (sv2v <files> > out.v && yosys -q -p 'read_verilog out.v; hierarchy -check -top soc_top'). A construct legal in SystemVerilog and not in Verilog-2005 passes lint and chip-level simulation and fails only there