GitHub organization
Agent skills by hdl-tools
- skills
- 17
- repository
- 1
Repositories by hdl-tools
Skills by hdl-tools, ranked
Ranked by score. Sort bymost stars,trending,newest,recently updated
| # | Skill | Repository | Stars | Used in | Tokens | Auto-check | Licence | Updated |
|---|---|---|---|---|---|---|---|---|
| 1 | Microarchitecture exploration, PPA estimation, risk assessment, and architecture sign-off for digital chip design. | hdl-tools/ | 212 | — | ~3.7k | Automated safety check: Notes | MIT | 5 days ago |
| 2 | Compiler toolchain development for custom processor ISAs — LLVM/GCC backend, assembler, linker scripts, runtime libraries, and regression validation. | hdl-tools/ | 212 | — | ~2.8k | Automated safety check: Notes | MIT | 5 days ago |
| 3 | 3.Dft Design for Test — scan architecture planning, scan insertion, ATPG pattern generation, MBIST for embedded memories, and JTAG boundary scan. | hdl-tools/ | 212 | — | ~3.3k | Automated safety check: Notes | MIT | 5 days ago |
| 4 | Embedded firmware and device drivers — BSP development, peripheral driver implementation (UART, SPI, I2C, GPIO, DMA, Timer), RTOS integration (FreeRTOS, Zephyr), and system validation. | hdl-tools/ | 212 | — | ~2.6k | Automated safety check: Notes | MIT | 5 days ago |
| 5 | Formal property verification (FPV) and logical equivalence checking (LEC). | hdl-tools/ | 212 | — | ~3.4k | Automated safety check: Notes | MIT | 5 days ago |
| 6 | FPGA prototyping — ASIC-to-FPGA RTL adaptation, multi-FPGA partitioning, synthesis and timing closure on FPGA, hardware bring-up, and software validation on the prototype. | hdl-tools/ | 212 | — | ~3.4k | Automated safety check: Notes | MIT | 5 days ago |
| 7 | UVM-based functional verification — testbench architecture, test planning, directed and constrained-random stimulus, functional and code coverage closure, formal assist, and regression sign-off. | hdl-tools/ | 212 | — | ~4.5k | Automated safety check: Notes | MIT | 5 days ago |
| 8 | 8.Hls High-Level Synthesis — C/C++ algorithm analysis, HLS directive optimisation, synthesis execution, and co-simulation verification. | hdl-tools/ | 212 | — | ~2.8k | Automated safety check: Notes | MIT | 5 days ago |
| 9 | Logic synthesis from RTL to gate-level netlist — SDC constraint validation, compile and optimisation strategy, netlist quality check, and LEC equivalence verification. | hdl-tools/ | 212 | — | ~2.7k | Automated safety check: Notes | MIT | 5 days ago |
| 10 | Full physical design flow — floorplan, placement, clock tree synthesis, routing, timing optimisation, power optimisation, area optimisation, and tape-out sign-off. | hdl-tools/ | 212 | — | ~3.8k | Automated safety check: Notes | MIT | 5 days ago |
| 11 | SoC IP integration — IP procurement and qualification, IP configuration, bus fabric setup, top-level RTL integration, and chip-level simulation. | hdl-tools/ | 212 | — | ~3k | Automated safety check: Notes | MIT | 5 days ago |
| 12 | 12.Sta Static timing analysis — multi-corner constraint validation, setup and hold analysis, timing exception review, and ECO guidance for closure. | hdl-tools/ | 212 | — | ~3.1k | Automated safety check: Notes | MIT | 5 days ago |
| 13 | EDA tool detection, wrapper deployment, and MCP configuration for digital chip design environments. | hdl-tools/ | 212 | — | ~18k | Automated safety check: Notes | MIT | 5 days ago |
| 14 | Embedded memory IP design — SRAM/register-file/ROM requirements capture, memory compiler and macro selection, array architecture (banking, ports, ECC wrapper), redundancy and repair allocation, view… | hdl-tools/ | 212 | — | ~5.6k | Automated safety check: Notes | MIT | 5 days ago |
| 15 | Cross-domain loop orchestration for the chip design pipeline. | hdl-tools/ | 212 | — | ~7.2k | Automated safety check: Notes | MIT | 5 days ago |
| 16 | 16.Rtl Design SystemVerilog RTL design — module planning, coding standards enforcement, lint checking, CDC/RDC analysis, and synthesis readiness verification. | hdl-tools/ | 212 | — | ~7k | Automated safety check: Notes | MIT | 5 days ago |
| 17 | Distil accumulated experience records (experiences.jsonl) into updated domain knowledge summaries (knowledge.md) for any chip-design domain. | hdl-tools/ | 212 | — | ~2.5k | Automated safety check: Notes | MIT | 5 days ago |
Questions, answered from the data.
What is the best skill by hdl-tools?
Architecture from hdl-tools/digital-chip-design-agents ranks first of the 17 skills by hdl-tools listed here, with the highest score: its repository has 212 GitHub stars, its SKILL.md loads about 3.7k tokens and it has informational notes only in the automated safety check. Next come Compiler Toolchain and Dft.
Are hdl-tools's skills official?
None yet. All 17 skills by hdl-tools listed here come from community repositories; a skill counts as official when the product's own GitHub organization publishes it.
How are these skills ranked?
By Skill Navigator score, which combines the GitHub stars of the skill's repository (shared across that repo's skills and discounted for large collections), how many other GitHub owners carry a copy of the skill, and automated SKILL.md quality checks, minus penalties for safety-check warnings and for each further skill from the same repository. Skills that fail the safety check are not listed.