Agent skill

Verilog Basics For Lowlevel

by mohitmishra786 in mohitmishra786/low-level-dev-skills

Verilog basics skill for firmware and kernel engineers. An agent skill from mohitmishra786/low-level-dev-skills.

MITAuto-check passedDevelopment

Install Verilog Basics For Lowlevel

skills CLI

$ npx skills add mohitmishra786/low-level-dev-skills --skill verilog-basics-for-lowlevel -a claude-code

Project install by default; add -g for ~/.claude/skills/.

GitHub CLI

$ gh skill install mohitmishra786/low-level-dev-skills verilog-basics-for-lowlevel --agent claude-code

Project scope by default; add --scope user for a personal install. Needs GitHub CLI 2.90.0 or later (public preview).

Manual copy

$ git clone --depth 1 https://github.com/mohitmishra786/low-level-dev-skills.git skills-src && mkdir -p .claude/skills && cp -r skills-src/skills/qemu/verilog-basics-for-lowlevel .claude/skills/verilog-basics-for-lowlevel && rm -rf skills-src

Use ~/.claude/skills/ instead of .claude/skills for a personal install. The folder must contain SKILL.md.

Claude Code skills documentation · loads skills from .claude/skills/

Paste into Claude Code

Install the "verilog-basics-for-lowlevel" agent skill from https://github.com/mohitmishra786/low-level-dev-skills/tree/main/skills/qemu/verilog-basics-for-lowlevel into .claude/skills/verilog-basics-for-lowlevel/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "verilog-basics-for-lowlevel", then confirm the skill loads.

Claude Code copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.

$skill-installer

$skill-installer install https://github.com/mohitmishra786/low-level-dev-skills/tree/main/skills/qemu/verilog-basics-for-lowlevel

Type this inside Codex. $skill-installer <name> installs a curated skill from openai/skills. The installer writes to $CODEX_HOME/skills (default ~/.codex/skills). Restart Codex if the skill does not show up.

skills CLI

$ npx skills add mohitmishra786/low-level-dev-skills --skill verilog-basics-for-lowlevel -a codex

Project install goes to .agents/skills/; add -g for ~/.codex/skills/.

GitHub CLI

$ gh skill install mohitmishra786/low-level-dev-skills verilog-basics-for-lowlevel --agent codex

Project scope by default (.agents/skills/); add --scope user for a personal install.

Manual copy

$ git clone --depth 1 https://github.com/mohitmishra786/low-level-dev-skills.git skills-src && mkdir -p .agents/skills && cp -r skills-src/skills/qemu/verilog-basics-for-lowlevel .agents/skills/verilog-basics-for-lowlevel && rm -rf skills-src

Use ~/.agents/skills/ instead of .agents/skills for a personal install.

Codex skills documentation · loads skills from .agents/skills/

Paste into Codex

Install the "verilog-basics-for-lowlevel" agent skill from https://github.com/mohitmishra786/low-level-dev-skills/tree/main/skills/qemu/verilog-basics-for-lowlevel into .agents/skills/verilog-basics-for-lowlevel/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "verilog-basics-for-lowlevel", then confirm the skill loads.

Codex copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.

skills CLI

$ npx skills add mohitmishra786/low-level-dev-skills --skill verilog-basics-for-lowlevel -a cursor

Project install goes to .agents/skills/; add -g for ~/.cursor/skills/.

GitHub CLI

$ gh skill install mohitmishra786/low-level-dev-skills verilog-basics-for-lowlevel --agent cursor

Project scope by default (.agents/skills/); add --scope user for a personal install.

Manual copy

$ git clone --depth 1 https://github.com/mohitmishra786/low-level-dev-skills.git skills-src && mkdir -p .cursor/skills && cp -r skills-src/skills/qemu/verilog-basics-for-lowlevel .cursor/skills/verilog-basics-for-lowlevel && rm -rf skills-src

Use ~/.cursor/skills/ instead of .cursor/skills for a personal install.

Cursor skills documentation · loads skills from .cursor/skills/, .agents/skills/, .claude/skills/, .codex/skills/

Paste into Cursor

Install the "verilog-basics-for-lowlevel" agent skill from https://github.com/mohitmishra786/low-level-dev-skills/tree/main/skills/qemu/verilog-basics-for-lowlevel into .cursor/skills/verilog-basics-for-lowlevel/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "verilog-basics-for-lowlevel", then confirm the skill loads.

Cursor copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.

gemini skills install

$ gemini skills install https://github.com/mohitmishra786/low-level-dev-skills.git --path skills/qemu/verilog-basics-for-lowlevel

--scope user (default) or --scope workspace; --path is the subfolder of the repo that holds the skill; --consent skips the security confirmation prompt.

skills CLI

$ npx skills add mohitmishra786/low-level-dev-skills --skill verilog-basics-for-lowlevel -a gemini-cli

Project install goes to .agents/skills/; add -g for ~/.gemini/skills/.

GitHub CLI

$ gh skill install mohitmishra786/low-level-dev-skills verilog-basics-for-lowlevel --agent gemini-cli

Project scope by default (.agents/skills/); add --scope user for a personal install.

Manual copy

$ git clone --depth 1 https://github.com/mohitmishra786/low-level-dev-skills.git skills-src && mkdir -p .gemini/skills && cp -r skills-src/skills/qemu/verilog-basics-for-lowlevel .gemini/skills/verilog-basics-for-lowlevel && rm -rf skills-src

Use ~/.gemini/skills/ instead of .gemini/skills for a personal install, then run /skills reload.

Gemini CLI skills documentation · loads skills from .gemini/skills/, .agents/skills/

Paste into Gemini CLI

Install the "verilog-basics-for-lowlevel" agent skill from https://github.com/mohitmishra786/low-level-dev-skills/tree/main/skills/qemu/verilog-basics-for-lowlevel into .gemini/skills/verilog-basics-for-lowlevel/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "verilog-basics-for-lowlevel", then confirm the skill loads.

Gemini CLI copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.

GitHub CLI

$ gh skill install mohitmishra786/low-level-dev-skills verilog-basics-for-lowlevel

Installs for Copilot at project scope by default; add --scope user for a personal install. Preview a skill first with gh skill preview. Needs GitHub CLI 2.90.0 or later (public preview).

skills CLI

$ npx skills add mohitmishra786/low-level-dev-skills --skill verilog-basics-for-lowlevel -a github-copilot

Project install goes to .agents/skills/; add -g for ~/.copilot/skills/.

Manual copy

$ git clone --depth 1 https://github.com/mohitmishra786/low-level-dev-skills.git skills-src && mkdir -p .github/skills && cp -r skills-src/skills/qemu/verilog-basics-for-lowlevel .github/skills/verilog-basics-for-lowlevel && rm -rf skills-src

Use ~/.copilot/skills/ instead of .github/skills for a personal install. Commit .github/skills so cloud agent and code review can use it.

GitHub Copilot skills documentation · loads skills from .github/skills/, .claude/skills/, .agents/skills/

Paste into GitHub Copilot

Install the "verilog-basics-for-lowlevel" agent skill from https://github.com/mohitmishra786/low-level-dev-skills/tree/main/skills/qemu/verilog-basics-for-lowlevel into .github/skills/verilog-basics-for-lowlevel/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "verilog-basics-for-lowlevel", then confirm the skill loads.

GitHub Copilot copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.

skills CLI

$ npx skills add mohitmishra786/low-level-dev-skills --skill verilog-basics-for-lowlevel -a opencode

OpenCode documents no install command of its own. Project install goes to .agents/skills/; add -g for ~/.config/opencode/skills/.

GitHub CLI

$ gh skill install mohitmishra786/low-level-dev-skills verilog-basics-for-lowlevel --agent opencode

Project scope by default (.agents/skills/); add --scope user for a personal install.

Manual copy

$ git clone --depth 1 https://github.com/mohitmishra786/low-level-dev-skills.git skills-src && mkdir -p .opencode/skills && cp -r skills-src/skills/qemu/verilog-basics-for-lowlevel .opencode/skills/verilog-basics-for-lowlevel && rm -rf skills-src

Use ~/.config/opencode/skills/ instead of .opencode/skills for a personal install.

OpenCode skills documentation · loads skills from .opencode/skills/, .claude/skills/, .agents/skills/

Paste into OpenCode

Install the "verilog-basics-for-lowlevel" agent skill from https://github.com/mohitmishra786/low-level-dev-skills/tree/main/skills/qemu/verilog-basics-for-lowlevel into .opencode/skills/verilog-basics-for-lowlevel/ in this project. Copy the whole folder (SKILL.md and every file beside it), keep the folder name "verilog-basics-for-lowlevel", then confirm the skill loads.

OpenCode copies the folder itself, the same result as the manual copy. Check what it changed before you commit it.

Facts

Skill name: verilog-basics-for-lowlevel
GitHub stars: 252
Token cost: ~891 tokens
SKILL.md length: 297 words
Files: 1
Skills in repo: 138
Repo updated: Jun 27, 2026
First seen: Oct 7, 2026
Licence: MIT

At a glance

Verilog basics skill for firmware and kernel engineers. An agent skill from mohitmishra786/low-level-dev-skills.

Works in 7 steps: Module structure → Synthesizable subset (what firmware… → Reset discipline → …
Reading RTL to understand hardware behavior
SKILL.md covers Purpose, When to Use, Workflow and Common Problems, plus 1 more section
Instructions only: no scripts, shell commands, URLs or credentials in SKILL.md

What it does

Verilog Basics For Lowlevel is an agent skill from mohitmishra786/low-level-dev-skills. Verilog basics skill for firmware and kernel engineers. Use when reading RTL to understand hardware behavior, reset/clock domains, bus protocols, or collaborating with hardware teams. Activates on queries about Verilog basics, RTL, hardware description, clock domain, reset synchronizer, or MMU in hardware.

Its SKILL.md is about 890 tokens, which your agent loads only when the skill is triggered. It is a single SKILL.md file with no bundled scripts.

It sits in Development. The repository describes itself as: A curated suite of AI agent skills for systems and low-level programming with C/C++, Rust, and Zig toolchains, covering compilers, debuggers, profilers, build systems…. The licence is MIT.

When your agent uses it

Reading RTL to understand hardware behavior
Reset/clock domains
Collaborating with hardware teams

Example prompts

“/verilog-basics-for-lowlevel”

Workflow steps

7 steps, taken from the step headings in SKILL.md.

Module structure
Synthesizable subset (what firmware folks need)
Reset discipline
Bus protocols (reading SoC diagrams)
Clock domains
Simulation vs silicon
Agent usage

What it can do on your machine

Read from SKILL.md and the folder at commit bdc5847. It shows what the files ask for, not the result of running them.

Tool permissions
Pre-approves nothing: there is no allowed-tools line, so your agent's usual permission prompts apply.
From allowed-tools in the SKILL.md frontmatter.
Runs code
No scripts in the folder and no shell commands in SKILL.md (its code samples are verilog and bash).
From the folder's file list and the shell code blocks in SKILL.md.
Network
No URLs in SKILL.md.
From URLs in SKILL.md, links to its own repository left out.
Credentials
Names no API keys, tokens, secrets or passwords.
From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.

Context cost

Verilog Basics For Lowlevel loads about 891 tokens when it runs. Until then it costs about 84 tokens; SKILL.md has 297 words of instructions outside code blocks.

Always · name and description, kept in context so the agent knows when to use it: ~84
When it runs · the whole SKILL.md, loaded when a task matches: ~891

Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.

Safety

Auto-check passed

The automated check found no risky patterns in SKILL.md.

Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.

SKILL.md

The full file from mohitmishra786/low-level-dev-skills at commit bdc5847, republished under its MIT licence (© mohitmishra786). 297 words, ~891 tokens.

Download SKILL.mdSave it as .claude/skills/verilog-basics-for-lowlevel/SKILL.md (or your agent's skills folder).

name: verilog-basics-for-lowlevel
description: Verilog basics skill for firmware and kernel engineers. Use when reading RTL to understand hardware behavior, reset/clock domains, bus protocols, or collaborating with hardware teams. Activates on queries about Verilog basics, RTL, hardware description, clock domain, reset synchronizer, or MMU in hardware.

Verilog Basics for Low-Level Engineers

Purpose

Give firmware and kernel engineers enough Verilog/SystemVerilog literacy to read RTL: modules, clocks/resets, combinational vs sequential logic, bus interfaces, and why hardware behavior explains driver bugs — not a replacement for HDL design courses.

When to Use

Reference manual unclear — RTL clarifies register behavior
Understanding CDC (clock domain crossing) bugs
Correlating DMA/AXI transactions with driver ordering
Reviewing SoC block diagram with hardware team

Workflow

1. Module structure

verilog

module uart_tx (
    input  wire       clk,
    input  wire       rst_n,   /* active-low async reset */
    input  wire       start,
    input  wire [7:0] data,
    output reg        busy
);
    /* sequential logic */
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            busy <= 1'b0;
        else if (start)
            busy <= 1'b1;
        /* ... */
    end
endmodule

wire = combinational/network; reg in always block = flip-flop unless combinational always @(*).

2. Synthesizable subset (what firmware folks need)

Construct	Meaning
`posedge clk`	Registered update
`assign x = a & b`	Combinational
`case` / `if` in `always @(*)`	Mux logic
Parameters `#(.WIDTH(32))`	Configurable width

Avoid #delay in synthesizable RTL — simulation only.

3. Reset discipline

Async assert, sync deassert common (rst_sync_n)
Firmware must wait post-reset setup times — see RM reset chapter
Multiple reset domains → peripheral may need explicit soft reset bit

4. Bus protocols (reading SoC diagrams)

Bus	Typical use
APB	Slow peripherals, simple reg interface
AHB	Higher throughput on-chip
AXI	DMA, modern SoCs — bursts, channels

Linux regmap MMIO maps to APB/AXI slave decode in RTL address map.

5. Clock domains

Signals crossing clk_a → clk_b need synchronizers (2+ FFs). Metastability causes intermittent firmware bugs — not fixed in software alone.

6. Simulation vs silicon

bash

# Typical open-source sim (conceptual)
iverilog -o sim.vvp design.v tb.v
vvp sim.vvp

QEMU/peripheral models may not match RTL edge cases.

7. Agent usage

/verilog-basics-for-lowlevel Explain this APB register block and when STATUS bit updates relative to WRITE

Common Problems

Symptom	Cause	Fix
Bit toggles once	Pulse in RTL	Poll latch / clear-on-read in driver
Random corruption	CDC	Hardware synchronizer; don't hack delays
Read stale data	Bus bridge buffer	Follow RM ordering / barrier
IRQ stuck	Level vs pulse in RTL	Match handler ACK sequence
Verilog vs VHDL	Mixed SoC docs	Focus on interface signals table

skills/baremetal/mmio-and-bit-manipulation — register access from C
skills/baremetal/peripherals-from-datasheet — RM ↔ RTL
skills/baremetal/datasheet-and-refmanual-reading — doc navigation
skills/kernel-dev/device-tree — hardware integration in Linux
skills/qemu/protocol-analysis — validate bus timing

Files

Just SKILL.md in skills/qemu/verilog-basics-for-lowlevel of mohitmishra786/low-level-dev-skills.

Open the folder on GitHubat commit bdc5847

Compare with similar skills

Verilog Basics For Lowlevel next to the 5 skills that share the most tags, products or categories with it. Stars are the repository's; “used in” counts other GitHub owners with a copy.

Verilog Basics For Lowlevel compared with similar skills
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Typescript Advanced Typesrolling-scopes/rsschool-app	10k	25 repos	~4.2k	Automated safety check: Pass	MPL-2.0	7 days ago
PR Babysitteropeninterpreter/openinterpreter	69k	3 repos	~4.2k	Automated safety check: Pass	Apache-2.0	today
Code Review ChecklistshareAI-lab/learn-claude-code	78k	4 repos	~1.1k	Automated safety check: Pass	MIT	12 days ago

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Questions about Verilog Basics For Lowlevel

What does Verilog Basics For Lowlevel do?

Verilog basics skill for firmware and kernel engineers. An agent skill from mohitmishra786/low-level-dev-skills. Verilog Basics For Lowlevel is an agent skill from mohitmishra786/low-level-dev-skills. Verilog basics skill for firmware and kernel engineers.

When should I use Verilog Basics For Lowlevel?

Verilog Basics For Lowlevel fits situations like: reading RTL to understand hardware behavior; reset/clock domains; collaborating with hardware teams.

How do I install Verilog Basics For Lowlevel in Claude Code?

Run `npx skills add mohitmishra786/low-level-dev-skills --skill verilog-basics-for-lowlevel -a claude-code`. Or copy the skill folder (skills/qemu/verilog-basics-for-lowlevel in mohitmishra786/low-level-dev-skills) into .claude/skills/verilog-basics-for-lowlevel in your project. Claude Code loads it when a task matches its description.

How do I install Verilog Basics For Lowlevel in Codex?

Run `npx skills add mohitmishra786/low-level-dev-skills --skill verilog-basics-for-lowlevel -a codex`. Or copy the skill folder (skills/qemu/verilog-basics-for-lowlevel in mohitmishra786/low-level-dev-skills) into .agents/skills/verilog-basics-for-lowlevel in your project. Codex loads it when a task matches its description.

Can I use Verilog Basics For Lowlevel in Cursor, Gemini CLI or GitHub Copilot?

Cursor, Gemini CLI, GitHub Copilot and OpenCode also load SKILL.md folders. With the skills CLI, run `npx skills add mohitmishra786/low-level-dev-skills --skill verilog-basics-for-lowlevel -a cursor` (or -a gemini-cli, github-copilot or opencode for the others). To copy it by hand, put the folder in .cursor/skills/verilog-basics-for-lowlevel, .gemini/skills/verilog-basics-for-lowlevel, .github/skills/verilog-basics-for-lowlevel and .opencode/skills/verilog-basics-for-lowlevel in your project.

What does Verilog Basics For Lowlevel need to run?

SKILL.md names no scripts, command-line tools or credentials: Verilog Basics For Lowlevel is instructions for the agent only.

Does Verilog Basics For Lowlevel access the network?

SKILL.md contains no URLs. Any network use would come from the scripts or tools the agent runs. This is read from the text; nothing was executed.

Is Verilog Basics For Lowlevel safe to install?

Our automated static check of SKILL.md found no risky patterns, such as piping downloads into a shell, reading credential files or hidden Unicode. It is not a guarantee. Review the folder before installing.

What licence does Verilog Basics For Lowlevel use?

Verilog Basics For Lowlevel is published under the MIT licence (the repository's licence). It allows redistribution, so the full SKILL.md is shown on this page.

How many tokens does Verilog Basics For Lowlevel use?

About 891 tokens (SKILL.md is roughly 3.6k characters). Agents keep only the skill's name and description in context until a task matches; then they load SKILL.md in full.

What are the alternatives to Verilog Basics For Lowlevel?

Skills that share tags, products or a category with Verilog Basics For Lowlevel: Vercel Composition Patterns (supabase/supabase, 111k stars), Finishing a Development Branch (obra/superpowers, 297k stars), Typescript Advanced Types (rolling-scopes/rsschool-app, 10k stars) and PR Babysitter (openinterpreter/openinterpreter, 69k stars). The comparison table on this page puts their stars, adoption, token cost, safety result and licence side by side.

Who maintains Verilog Basics For Lowlevel?

mohitmishra786 (a GitHub user) maintains it in mohitmishra786/low-level-dev-skills, which has 252 GitHub stars. The repository holds 138 skills in this directory. The repository was last updated on June 27, 2026.

Source: mohitmishra786/low-level-dev-skills on GitHub. Facts on this page come from the repository at the commit we read; the author's words are quoted as theirs.

Install Verilog Basics For Lowlevel

Facts

At a glance

What it does

When your agent uses it

Example prompts

Workflow steps

What it can do on your machine

Tool permissions

Runs code

Network

Credentials

Context cost

Safety

SKILL.md

Verilog Basics for Low-Level Engineers

Purpose

When to Use

Workflow

1. Module structure

2. Synthesizable subset (what firmware folks need)

3. Reset discipline

4. Bus protocols (reading SoC diagrams)

5. Clock domains

6. Simulation vs silicon

7. Agent usage

Common Problems

Related Skills

Files

Compare with similar skills

Similar skills

More from mohitmishra786/low-level-dev-skills

Related

Questions about Verilog Basics For Lowlevel