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Agent skill

RISC-V Assembly Guide

by mohitmishra786 in mohitmishra786/low-level-dev-skills

Reference for RISC-V assembly on RV32 and RV64: register names and calling convention, extension naming, GCC and Clang inline asm, and QEMU with GDB debugging.

MITAuto-check passedDevelopment

Install RISC-V Assembly Guide

skills CLI
$ npx skills add mohitmishra786/low-level-dev-skills --skill assembly-riscv -a claude-code

Project install by default; add -g for ~/.claude/skills/.

GitHub CLI
$ gh skill install mohitmishra786/low-level-dev-skills assembly-riscv --agent claude-code

Project scope by default; add --scope user for a personal install. Needs GitHub CLI 2.90.0 or later (public preview).

Manual copy
$ git clone --depth 1 https://github.com/mohitmishra786/low-level-dev-skills.git skills-src && mkdir -p .claude/skills && cp -r skills-src/skills/low-level-programming/assembly-riscv .claude/skills/assembly-riscv && rm -rf skills-src

Use ~/.claude/skills/ instead of .claude/skills for a personal install. The folder must contain SKILL.md.

Claude Code skills documentation · loads skills from .claude/skills/

Facts

Skill name
assembly-riscv
GitHub stars
252
Token cost
~1.8k tokens
SKILL.md length
352 words
Files
2 (incl. references)
Skills in repo
138
Repo updated
First seen
Licence
MIT

At a glance

Reference for RISC-V assembly on RV32 and RV64: register names and calling convention, extension naming, GCC and Clang inline asm, and QEMU with GDB debugging.

  • Works in 7 steps: Register file and calling convention → Basic instructions → Minimal function (psABI calling… → …
  • Writing a RISC-V assembly routine that follows the calling convention
  • SKILL.md covers Purpose, Triggers, Workflow and Related skills
  • Calls apt-get

What it does

This skill covers writing and reading RISC-V assembly for RV32 and RV64. It lists the 32 integer registers with their ABI names, roles and which side saves them, the floating-point registers, basic instruction forms and a minimal function that follows the psABI calling convention, with arguments in a0 and a1 and the return value in a0.

It also explains how extension letters combine after the base ISA, from I, M, A, F, D and C to G as shorthand for IMAFD, plus the vector, Zicsr, Zifencei, bit-manipulation and Ztso extensions. The description adds inline assembly with GCC and Clang, compressed instructions, and simulating a program with QEMU while debugging it through GDB remote. A reference file on the RISC-V ABI is included.

When your agent uses it

  • Writing a RISC-V assembly routine that follows the calling convention
  • Working out what an extension string such as rv64gc means
  • Embedding inline assembly in C for a RISC-V target
  • Running and debugging RISC-V code under QEMU and GDB

Example prompts

  • “Write a RISC-V function that adds two ints following the psABI and show which registers it uses.”
  • “What do the letters in rv32imac stand for?”
  • “How do I run this RISC-V binary in QEMU and attach GDB?”

Requirements

  • QEMU and GDB for simulation and debugging

Workflow steps

7 steps, taken from the step headings in SKILL.md.

  1. Register file and calling convention
  2. Basic instructions
  3. Minimal function (psABI calling convention)
  4. ISA extension naming
  5. Inline assembly (GCC/Clang)
  6. Compressed instructions (RVC)
  7. QEMU simulation and GDB

What it can do on your machine

Read from SKILL.md and the folder at commit bdc5847. It shows what the files ask for, not the result of running them.

  • Tool permissions

    Pre-approves nothing: there is no allowed-tools line, so your agent's usual permission prompts apply.

    From allowed-tools in the SKILL.md frontmatter.

  • Runs code

    Shell commands in SKILL.md call:

    • apt-get

    From the folder's file list and the shell code blocks in SKILL.md.

  • Network

    No URLs in SKILL.md.

    From URLs in SKILL.md, links to its own repository left out.

  • Credentials

    Names no API keys, tokens, secrets or passwords.

    From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.

Context cost

RISC-V Assembly Guide loads about 1.8k tokens when it runs, and up to ~2.7k if it reads all its reference files. Until then it costs about 108 tokens; SKILL.md has 352 words of instructions outside code blocks.

Always · name and description, kept in context so the agent knows when to use it
~108
When it runs · the whole SKILL.md, loaded when a task matches
~1.8k
With references · SKILL.md plus every file in references/, read only if the agent opens them
~2.7k

Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.

Safety

Auto-check passed

The automated check found no risky patterns in SKILL.md.

Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.

SKILL.md

The full file from mohitmishra786/low-level-dev-skills at commit bdc5847, republished under its MIT licence (© mohitmishra786). 352 words, ~1,817 tokens.

Download SKILL.mdSave it as .claude/skills/assembly-riscv/SKILL.md (or your agent's skills folder). This skill also uses 1 other file; get the full folder from GitHub.
name
assembly-riscv
description
RISC-V assembly skill for RV32/RV64 programming. Use when working with the RISC-V ISA, calling conventions (psABI), inline assembly with GCC/Clang, understanding extension naming (IMAFD), compressed instructions, or simulating RISC-V with QEMU and GDB remote debugging. Activates on queries about RISC-V assembly, RV32, RV64, RISC-V calling convention, RISC-V inline asm, RISC-V extensions, QEMU RISC-V, or RISC-V GDB.

RISC-V Assembly

Purpose

Guide agents through RISC-V assembly programming: RV32/RV64 instruction sets, register naming and calling conventions (psABI), ISA extension naming, inline assembly with GCC/Clang, compressed (RVC) instructions, and QEMU-based simulation with GDB remote debugging.

Triggers

  • "How do I write RISC-V assembly?"
  • "What are the RISC-V calling convention registers?"
  • "How do I use inline asm for RISC-V in C?"
  • "What do RISC-V extension letters mean (IMAFD)?"
  • "How do I simulate RISC-V with QEMU?"
  • "How do I debug RISC-V code with GDB?"

Workflow

1. Register file and calling convention

RISC-V has 32 integer registers (x0–x31) with ABI names:

RegisterABI nameRoleSaved by
x0zeroHard-wired zero—
x1raReturn addressCaller
x2spStack pointerCallee
x3gpGlobal pointer—
x4tpThread pointer—
x5–x7t0–t2TemporariesCaller
x8s0/fpFrame pointerCallee
x9s1Saved registerCallee
x10–x11a0–a1Arguments / return valuesCaller
x12–x17a2–a7ArgumentsCaller
x18–x27s2–s11Saved registersCallee
x28–x31t3–t6TemporariesCaller

Floating-point registers (F extension): f0–f31 (fa0–fa7 for arguments).

2. Basic instructions
asm
# Arithmetic (R and I type)
add   a0, a1, a2      # a0 = a1 + a2
sub   a0, a1, a2      # a0 = a1 - a2
addi  a0, a1, 42      # a0 = a1 + 42 (immediate)
mul   a0, a1, a2      # a0 = a1 * a2 (M extension)
div   a0, a1, a2      # signed divide (M extension)
rem   a0, a1, a2      # remainder (M extension)

# Logical
and   a0, a1, a2      # bitwise AND
or    a0, a1, a2      # bitwise OR
xor   a0, a1, a2      # bitwise XOR
sll   a0, a1, a2      # shift left logical
srl   a0, a1, a2      # shift right logical (unsigned)
sra   a0, a1, a2      # shift right arithmetic (signed)

# Load / store
lw    a0, 0(sp)       # load word (32-bit)
ld    a0, 0(sp)       # load doubleword (64-bit, RV64)
lh    a0, 4(sp)       # load halfword (sign-extended)
lbu   a0, 8(sp)       # load byte (zero-extended)
sw    a0, 0(sp)       # store word
sd    a0, 0(sp)       # store doubleword (RV64)

# Branches (compare and branch)
beq   a0, a1, label   # branch if equal
bne   a0, a1, label   # branch if not equal
blt   a0, a1, label   # branch if less than (signed)
bltu  a0, a1, label   # branch if less than (unsigned)
bge   a0, a1, label   # branch if ≥ (signed)

# Jumps
j     label           # unconditional jump (pseudoinstruction: jal x0, label)
jal   ra, func        # jump and link (call)
jalr  zero, ra, 0     # jump to ra (return: pseudoinstruction: ret)
3. Minimal function (psABI calling convention)
asm
.section .text
.global add_numbers
# int add_numbers(int a, int b);  — a in a0, b in a1, return in a0
add_numbers:
    add   a0, a0, a1   # result = a + b
    ret                # return (jalr zero, ra, 0)

.global factorial
# long factorial(int n);  — n in a0
factorial:
    addi  sp, sp, -16      # allocate stack frame
    sd    ra, 8(sp)        # save return address (RV64)
    sd    s0, 0(sp)        # save s0 (callee-saved)

    mv    s0, a0           # s0 = n
    li    a0, 1            # default return 1
    blez  s0, .done        # if n <= 0, return 1

    addi  a0, s0, -1      # a0 = n - 1
    call  factorial        # recursive call: factorial(n-1)
    mul   a0, a0, s0       # a0 = result * n

.done:
    ld    ra, 8(sp)        # restore ra
    ld    s0, 0(sp)        # restore s0
    addi  sp, sp, 16       # deallocate
    ret
Show full SKILL.md (177 more words)Show less
4. ISA extension naming

RISC-V extensions are combined as a string after the base ISA:

LetterExtensionDescription
IIntegerBase 32/64-bit integer (RV32I, RV64I)
MMultiplyInteger multiply and divide
AAtomicAtomic memory operations (lr/sc, AMOs)
FFloatSingle-precision float
DDoubleDouble-precision float
CCompressed16-bit compressed instructions
GGeneral= IMAFD (shorthand)
VVectorVector instructions (SIMD)
ZicsrCSRControl/status register access
ZifenceiFence.iInstruction-fetch fence
Zba/Zbb/Zbc/ZbsBit manipulationBit ops (B extension set)
ZtsoTSOTotal Store Ordering memory model

Common targets:

  • Embedded: rv32imac — no floating point, with atomics and compressed
  • Linux app: rv64gc — full general + compressed
  • High performance: rv64gcv — + vector
5. Inline assembly (GCC/Clang)
c
// Read a CSR register (e.g., cycle counter)
static inline uint64_t read_cycle(void) {
    uint64_t val;
    asm volatile ("rdcycle %0" : "=r"(val));
    return val;
}

// Atomic swap
static inline int atomic_swap(int *ptr, int new_val) {
    int old;
    asm volatile (
        "amoswap.w.aqrl %0, %2, (%1)"
        : "=r"(old)
        : "r"(ptr), "r"(new_val)
        : "memory"
    );
    return old;
}

// Memory fence
static inline void memory_fence(void) {
    asm volatile ("fence rw, rw" ::: "memory");
}

// CSR read/write
#define csr_read(csr) ({                    \
    uint64_t _v;                            \
    asm volatile ("csrr %0, " #csr : "=r"(_v)); \
    _v;                                     \
})

uint64_t mstatus = csr_read(mstatus);
6. Compressed instructions (RVC)

RVC replaces common 32-bit instructions with 16-bit versions when:

  • Register is in x8–x15 (for c. versions)
  • Immediate fits in smaller field
  • Specific instruction patterns match
bash
# Enable C extension in GCC
riscv64-linux-gnu-gcc -march=rv64gc prog.c -o prog

# Check if compressed instructions were generated
riscv64-linux-gnu-objdump -d prog | grep "c\."
# c.addi, c.ld, c.sw, c.j, etc.

# Disable compressed (for debugging or targets without C)
riscv64-linux-gnu-gcc -march=rv64g prog.c -o prog
7. QEMU simulation and GDB
bash
# Install QEMU RISC-V
apt-get install qemu-user qemu-system-riscv64

# User-mode emulation (run RV64 binary on x86 host)
qemu-riscv64 ./prog

# System emulation (full bare-metal VM)
qemu-system-riscv64 \
  -machine virt \
  -nographic \
  -kernel firmware.elf \
  -gdb tcp::1234 \
  -S     # start paused

# GDB remote session
riscv64-linux-gnu-gdb prog
(gdb) target remote :1234
(gdb) load
(gdb) break main
(gdb) continue

For the RISC-V psABI calling convention details, see references/riscv-abi.md.

  • Use skills/low-level-programming/assembly-arm for AArch64 comparison
  • Use skills/low-level-programming/assembly-x86 for x86-64 assembly
  • Use skills/embedded/openocd-jtag for real hardware RISC-V debugging
  • Use skills/compilers/cross-gcc for RISC-V cross-compilation setup

© mohitmishra786, MIT. Rendered from Markdown: HTML in the file is shown as text, images as links, and headings moved down two levels. Raw file

Files

SKILL.md and 1 other file (references) in skills/low-level-programming/assembly-riscv of mohitmishra786/low-level-dev-skills.

  • SKILL.md
  • references/riscv-abi.md

Open the folder on GitHubat commit bdc5847

Compare with similar skills

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Meatloaf Networkingidolpx/meatloaf128—~7.1kAutomated safety check: PassGPL-3.0

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Categories

Questions about RISC-V Assembly Guide

What does RISC-V Assembly Guide do?

Reference for RISC-V assembly on RV32 and RV64: register names and calling convention, extension naming, GCC and Clang inline asm, and QEMU with GDB debugging. This skill covers writing and reading RISC-V assembly for RV32 and RV64. It lists the 32 integer registers with their ABI names, roles and which side saves them, the floating-point registers, basic instruction forms and a minimal function that follows the psABI calling convention, with arguments in a0 and a1 and the return value in a0.

When should I use RISC-V Assembly Guide?

RISC-V Assembly Guide fits situations like: writing a RISC-V assembly routine that follows the calling convention; working out what an extension string such as rv64gc means; embedding inline assembly in C for a RISC-V target; running and debugging RISC-V code under QEMU and GDB.

How do I install RISC-V Assembly Guide in Claude Code?

Run `npx skills add mohitmishra786/low-level-dev-skills --skill assembly-riscv -a claude-code`. Or copy the skill folder (skills/low-level-programming/assembly-riscv in mohitmishra786/low-level-dev-skills) into .claude/skills/assembly-riscv in your project. Claude Code loads it when a task matches its description.

How do I install RISC-V Assembly Guide in Codex?

Run `npx skills add mohitmishra786/low-level-dev-skills --skill assembly-riscv -a codex`. Or copy the skill folder (skills/low-level-programming/assembly-riscv in mohitmishra786/low-level-dev-skills) into .agents/skills/assembly-riscv in your project. Codex loads it when a task matches its description.

Can I use RISC-V Assembly Guide in Cursor, Gemini CLI or GitHub Copilot?

Cursor, Gemini CLI, GitHub Copilot and OpenCode also load SKILL.md folders. With the skills CLI, run `npx skills add mohitmishra786/low-level-dev-skills --skill assembly-riscv -a cursor` (or -a gemini-cli, github-copilot or opencode for the others). To copy it by hand, put the folder in .cursor/skills/assembly-riscv, .gemini/skills/assembly-riscv, .github/skills/assembly-riscv and .opencode/skills/assembly-riscv in your project.

What does RISC-V Assembly Guide need to run?

Going by SKILL.md and its folder, RISC-V Assembly Guide needs the command-line tools its instructions call (apt-get). Our summary lists: QEMU and GDB for simulation and debugging.

Does RISC-V Assembly Guide access the network?

SKILL.md contains no URLs. Any network use would come from the scripts or tools the agent runs. This is read from the text; nothing was executed.

Is RISC-V Assembly Guide safe to install?

Our automated static check of SKILL.md found no risky patterns, such as piping downloads into a shell, reading credential files or hidden Unicode. It is not a guarantee. Review the folder before installing.

What licence does RISC-V Assembly Guide use?

RISC-V Assembly Guide is published under the MIT licence (the repository's licence). It allows redistribution, so the full SKILL.md is shown on this page.

How many tokens does RISC-V Assembly Guide use?

About 1.8k tokens (SKILL.md is roughly 7.3k characters). Agents keep only the skill's name and description in context until a task matches; then they load SKILL.md in full. Its references folder adds about 909 tokens, read only when the agent opens those files.

What are the alternatives to RISC-V Assembly Guide?

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Who maintains RISC-V Assembly Guide?

mohitmishra786 (a GitHub user) maintains it in mohitmishra786/low-level-dev-skills, which has 252 GitHub stars. The repository holds 138 skills in this directory. The repository was last updated on June 27, 2026.

Source: mohitmishra786/low-level-dev-skills on GitHub. Facts on this page come from the repository at the commit we read; the author's words are quoted as theirs.