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Agent skill

ARM and AArch64 Assembly

by mohitmishra786 in mohitmishra786/low-level-dev-skills

Guides reading and writing AArch64 and ARM Thumb assembly: compiler output, inline asm, registers, the AAPCS calling convention and NEON or SVE basics.

MITAuto-check passedDevelopment

Install ARM and AArch64 Assembly

skills CLI
$ npx skills add mohitmishra786/low-level-dev-skills --skill assembly-arm -a claude-code

Project install by default; add -g for ~/.claude/skills/.

GitHub CLI
$ gh skill install mohitmishra786/low-level-dev-skills assembly-arm --agent claude-code

Project scope by default; add --scope user for a personal install. Needs GitHub CLI 2.90.0 or later (public preview).

Manual copy
$ git clone --depth 1 https://github.com/mohitmishra786/low-level-dev-skills.git skills-src && mkdir -p .claude/skills && cp -r skills-src/skills/low-level-programming/assembly-arm .claude/skills/assembly-arm && rm -rf skills-src

Use ~/.claude/skills/ instead of .claude/skills for a personal install. The folder must contain SKILL.md.

Claude Code skills documentation · loads skills from .claude/skills/

Facts

Skill name
assembly-arm
GitHub stars
252
Token cost
~1.9k tokens
SKILL.md length
619 words
Files
2 (incl. references)
Skills in repo
138
Repo updated
First seen
Licence
MIT

At a glance

Guides reading and writing AArch64 and ARM Thumb assembly: compiler output, inline asm, registers, the AAPCS calling convention and NEON or SVE basics.

  • Works in 11 steps: Generate ARM assembly → AArch64 registers (AAPCS64) → AAPCS64 calling convention → …
  • Reading GCC or Clang assembly output for an AArch64 target
  • SKILL.md covers Purpose, Triggers, Workflow and Related skills
  • Instructions only: no scripts, shell commands, URLs or credentials in SKILL.md

What it does

An agent is guided through AArch64 and 32-bit ARM Thumb assembly: reading compiler output, writing inline asm in C or C++ and understanding the ARM calling conventions AAPCS64 and AAPCS. It also covers debugging register and stack state on ARM hardware or QEMU.

The workflow shows how to generate assembly with a cross-compiler such as aarch64-linux-gnu-gcc -S, lists the AArch64 register set with roles, aliases and width variants, and summarizes the AAPCS64 rules: arguments in x0 to x7, SIMD arguments in v0 to v7, the callee-saved ranges and a stack that must be 16-byte aligned at calls. A table of common instructions explains moves, loads and stores, pair loads and arithmetic, and NEON and SVE SIMD patterns are included. A references/reference.md file holds more detail.

When your agent uses it

  • Reading GCC or Clang assembly output for an AArch64 target
  • Writing inline asm in C or C++ for ARM
  • Looking up AAPCS64 registers and the calling convention
  • Debugging register and stack state under QEMU

Example prompts

  • “Compile foo.c to AArch64 assembly with -O2 and explain what the loop does.”
  • “Write an inline asm snippet in C for AArch64 that adds two integers.”
  • “Which registers are callee-saved under AAPCS64?”

Requirements

  • An AArch64 cross-compiler such as aarch64-linux-gnu-gcc
  • QEMU or ARM hardware for running and debugging

Workflow steps

11 steps, taken from the step headings in SKILL.md.

  1. Generate ARM assembly
  2. AArch64 registers (AAPCS64)
  3. AAPCS64 calling convention
  4. Common AArch64 instructions
  5. Typical function prologue/epilogue
  6. Inline assembly (GCC/Clang)
  7. NEON SIMD intrinsics
  8. Darwin vs Linux AArch64 ABI differences
  9. AMX primer (Apple Silicon)
  10. 16KB page size on Apple M-series
  11. NEON → SVE2 migration hints

What it can do on your machine

Read from SKILL.md and the folder at commit bdc5847. It shows what the files ask for, not the result of running them.

  • Tool permissions

    Pre-approves nothing: there is no allowed-tools line, so your agent's usual permission prompts apply.

    From allowed-tools in the SKILL.md frontmatter.

  • Runs code

    No scripts in the folder and no shell commands in SKILL.md (its code samples are c, bash and asm).

    From the folder's file list and the shell code blocks in SKILL.md.

  • Network

    No URLs in SKILL.md.

    From URLs in SKILL.md, links to its own repository left out.

  • Credentials

    Names no API keys, tokens, secrets or passwords.

    From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.

Context cost

ARM and AArch64 Assembly loads about 1.9k tokens when it runs, and up to ~3.3k if it reads all its reference files. Until then it costs about 108 tokens; SKILL.md has 619 words of instructions outside code blocks.

Always · name and description, kept in context so the agent knows when to use it
~108
When it runs · the whole SKILL.md, loaded when a task matches
~1.9k
With references · SKILL.md plus every file in references/, read only if the agent opens them
~3.3k

Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.

Safety

Auto-check passed

The automated check found no risky patterns in SKILL.md.

Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.

SKILL.md

The full file from mohitmishra786/low-level-dev-skills at commit bdc5847, republished under its MIT licence (© mohitmishra786). 619 words, ~1,910 tokens.

Download SKILL.mdSave it as .claude/skills/assembly-arm/SKILL.md (or your agent's skills folder). This skill also uses 1 other file; get the full folder from GitHub.
name
assembly-arm
description
AArch64 and ARM assembly skill for reading and writing ARM assembly code. Use when reading GCC/Clang output for AArch64 or ARM Thumb targets, writing inline asm in C/C++, understanding the ARM ABI (AAPCS64/AAPCS), or debugging register and stack state on ARM hardware or QEMU. Activates on queries about AArch64 assembly, ARM Thumb, NEON/SVE SIMD, ARM calling convention, inline asm for ARM, or reading ARM disassembly.

ARM / AArch64 Assembly

Purpose

Guide agents through AArch64 (64-bit) and ARM (32-bit Thumb) assembly: registers, calling conventions, inline asm, and NEON/SVE SIMD patterns.

Triggers

  • "How do I read ARM64 assembly output?"
  • "What are the AArch64 registers and calling convention?"
  • "How do I write inline asm for ARM?"
  • "What is the difference between AArch64 and ARM Thumb?"
  • "How do I use NEON intrinsics?"

Workflow

1. Generate ARM assembly
bash
# AArch64 (native or cross-compile)
aarch64-linux-gnu-gcc -S -O2 foo.c -o foo.s

# 32-bit ARM Thumb
arm-linux-gnueabihf-gcc -S -O2 -mthumb foo.c -o foo.s

# From objdump
aarch64-linux-gnu-objdump -d -S prog

# From GDB on target
(gdb) disassemble /s main
2. AArch64 registers (AAPCS64)
RegisterAliasRole
x0–x7—Arguments 1–8 and return values
x8xrIndirect result location (struct return)
x9–x15—Caller-saved temporaries
x16–x17ip0, ip1Intra-procedure-call temporaries (used by linker)
x18prPlatform register (reserved on some OS)
x19–x28—Callee-saved
x29fpFrame pointer (callee-saved)
x30lrLink register (return address)
sp—Stack pointer (must be 16-byte aligned at call)
pc—Program counter (not directly accessible)
xzrwzrZero register (reads as 0, writes discarded)
v0–v7q0–q7FP/SIMD args and return
v8–v15—Callee-saved SIMD (lower 64 bits only)
v16–v31—Caller-saved temporaries

Width variants: x0 (64-bit), w0 (32-bit, zero-extends to 64), h0 (16), b0 (8).

3. AAPCS64 calling convention

Integer/pointer args: x0–x7 Float/SIMD args: v0–v7 Return: x0 (int), x0+x1 (128-bit), v0 (float/SIMD) Callee-saved: x19–x28, x29 (fp), x30 (lr), v8–v15 (lower 64 bits) Caller-saved: everything else

Stack must be 16-byte aligned at any bl or blr instruction.

4. Common AArch64 instructions
InstructionEffect
mov x0, x1Copy register
mov x0, #42Load immediate
movz x0, #0x1234, lsl #16Move zero-extended with shift
movk x0, #0xabcdMove with keep (partial update)
ldr x0, [x1]Load 64-bit from address in x1
ldr x0, [x1, #8]Load from x1+8
str x0, [x1, #8]Store x0 to x1+8
ldp x0, x1, [sp, #16]Load pair (two regs at once)
stp x29, x30, [sp, #-16]!Store pair, pre-decrement sp
add x0, x1, x2x0 = x1 + x2
add x0, x1, #8x0 = x1 + 8
sub x0, x1, x2x0 = x1 - x2
mul x0, x1, x2x0 = x1 * x2
sdiv x0, x1, x2Signed divide
udiv x0, x1, x2Unsigned divide
cmp x0, x1Set flags for x0 - x1
cbz x0, labelBranch if x0 == 0
cbnz x0, labelBranch if x0 != 0
bl funcBranch with link (call)
blr x0Branch with link to address in x0
retReturn (branch to x30)
ret x0Return to address in x0
adrp x0, symbolPC-relative page address
add x0, x0, :lo12:symbolLow 12 bits of symbol offset
Show full SKILL.md (224 more words)Show less
5. Typical function prologue/epilogue
asm
// Non-leaf function
stp  x29, x30, [sp, #-32]!   // save fp, lr; allocate 32 bytes
mov  x29, sp                  // set frame pointer
stp  x19, x20, [sp, #16]     // save callee-saved registers
// ... body ...
ldp  x19, x20, [sp, #16]     // restore
ldp  x29, x30, [sp], #32     // restore fp, lr; deallocate
ret

// Leaf function (no calls, no callee-saved regs needed)
// Can use red zone (no rsp adjustment) — but AArch64 has no red zone
sub  sp, sp, #16             // allocate locals
// ... body ...
add  sp, sp, #16
ret
6. Inline assembly (GCC/Clang)
c
// Barrier
__asm__ volatile ("dmb ish" ::: "memory");

// Load acquire
static inline int load_acquire(volatile int *p) {
    int val;
    __asm__ volatile ("ldar %w0, %1" : "=r"(val) : "Q"(*p));
    return val;
}

// Store release
static inline void store_release(volatile int *p, int val) {
    __asm__ volatile ("stlr %w1, %0" : "=Q"(*p) : "r"(val));
}

// Read system counter
static inline uint64_t read_cntvct(void) {
    uint64_t val;
    __asm__ volatile ("mrs %0, cntvct_el0" : "=r"(val));
    return val;
}

AArch64-specific constraints:

  • "Q" — memory operand suitable for exclusive/acquire/release instructions
  • "r" — any general-purpose register
  • "w" — any FP/SIMD register
7. NEON SIMD intrinsics
c
#include <arm_neon.h>

// Add 4 floats at once
float32x4_t a = vld1q_f32(arr_a);   // load 4 floats
float32x4_t b = vld1q_f32(arr_b);
float32x4_t c = vaddq_f32(a, b);
vst1q_f32(result, c);

// Horizontal sum
float32x4_t sum = vpaddq_f32(c, c);
sum = vpaddq_f32(sum, sum);
float total = vgetq_lane_f32(sum, 0);

Naming convention: v<op><q>_<type>

  • q suffix: 128-bit (quad) vector
  • _f32: float32, _s32: int32, _u8: uint8, etc.
8. Darwin vs Linux AArch64 ABI differences
AspectLinux (AAPCS64)Apple Darwin (arm64)
Stack alignment16 bytes at public interfaces16 bytes
Red zone128 bytes below SPNo red zone
x18 registerPlatform reserved (TLS)Platform register (do not use)
Varargsx0–x7, then stackSame, but different objc_msgSend conventions
Name manglingItanium C++ ABISame + Apple blocks

On macOS/iOS, avoid using x18; use _DARWIN_C_LEVEL headers for platform types.

9. AMX primer (Apple Silicon)

Apple Matrix coprocessor (AMX) is not exposed via public intrinsics. Access paths:

c
// Practical: Accelerate/vecLib uses AMX internally
#include <Accelerate/Accelerate.h>
// cblas_sgemm, vDSP_* dispatch to AMX on M-series

// Low-level: community-documented opcodes — not portable, avoid in production

Prefer Metal Performance Shaders or Accelerate for matrix workloads on Apple Silicon (skills/platform/apple-silicon).

10. 16KB page size on Apple M-series

macOS on Apple Silicon uses 16KB pages (not 4KB):

c
#include <unistd.h>
long page = sysconf(_SC_PAGESIZE);  // 16384 on macOS arm64
// Align mmap and posix_memalign to page size

Code assuming PAGE_SIZE == 4096 may misalign buffers or fail mmap on macOS.

11. NEON → SVE2 migration hints
Porting checklist
├── Replace 128-bit fixed loops with svcnt*() strides on SVE hardware
├── Use predicates (svwhilelt) for tails instead of scalar epilogues
├── Guard SVE code with #ifdef __ARM_FEATURE_SVE
└── Keep NEON path for Apple M1–M3 (no SVE); use SVE2 on Graviton/M4+

See skills/platform/arm-sve for SVE intrinsics and auto-vectorization flags.

For a register reference, see references/reference.md.

  • Use skills/low-level-programming/assembly-x86 for x86-64 assembly
  • Use skills/compilers/cross-gcc for cross-compilation toolchain
  • Use skills/debuggers/gdb for debugging ARM code with gdbserver
  • Use skills/platform/arm-sve for SVE/SVE2 scalable vectors
  • Use skills/platform/apple-silicon for M-series unified memory and AMX

© mohitmishra786, MIT. Rendered from Markdown: HTML in the file is shown as text, images as links, and headings moved down two levels. Raw file

Files

SKILL.md and 1 other file (references) in skills/low-level-programming/assembly-arm of mohitmishra786/low-level-dev-skills.

  • SKILL.md
  • references/reference.md

Open the folder on GitHubat commit bdc5847

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Works with

Categories

Questions about ARM and AArch64 Assembly

What does ARM and AArch64 Assembly do?

Guides reading and writing AArch64 and ARM Thumb assembly: compiler output, inline asm, registers, the AAPCS calling convention and NEON or SVE basics. An agent is guided through AArch64 and 32-bit ARM Thumb assembly: reading compiler output, writing inline asm in C or C++ and understanding the ARM calling conventions AAPCS64 and AAPCS. It also covers debugging register and stack state on ARM hardware or QEMU.

When should I use ARM and AArch64 Assembly?

ARM and AArch64 Assembly fits situations like: reading GCC or Clang assembly output for an AArch64 target; writing inline asm in C or C++ for ARM; looking up AAPCS64 registers and the calling convention; debugging register and stack state under QEMU.

How do I install ARM and AArch64 Assembly in Claude Code?

Run `npx skills add mohitmishra786/low-level-dev-skills --skill assembly-arm -a claude-code`. Or copy the skill folder (skills/low-level-programming/assembly-arm in mohitmishra786/low-level-dev-skills) into .claude/skills/assembly-arm in your project. Claude Code loads it when a task matches its description.

How do I install ARM and AArch64 Assembly in Codex?

Run `npx skills add mohitmishra786/low-level-dev-skills --skill assembly-arm -a codex`. Or copy the skill folder (skills/low-level-programming/assembly-arm in mohitmishra786/low-level-dev-skills) into .agents/skills/assembly-arm in your project. Codex loads it when a task matches its description.

Can I use ARM and AArch64 Assembly in Cursor, Gemini CLI or GitHub Copilot?

Cursor, Gemini CLI, GitHub Copilot and OpenCode also load SKILL.md folders. With the skills CLI, run `npx skills add mohitmishra786/low-level-dev-skills --skill assembly-arm -a cursor` (or -a gemini-cli, github-copilot or opencode for the others). To copy it by hand, put the folder in .cursor/skills/assembly-arm, .gemini/skills/assembly-arm, .github/skills/assembly-arm and .opencode/skills/assembly-arm in your project.

What does ARM and AArch64 Assembly need to run?

SKILL.md names no scripts, command-line tools or credentials: ARM and AArch64 Assembly is instructions for the agent only. Our summary lists: An AArch64 cross-compiler such as aarch64-linux-gnu-gcc; QEMU or ARM hardware for running and debugging.

Does ARM and AArch64 Assembly access the network?

SKILL.md contains no URLs. Any network use would come from the scripts or tools the agent runs. This is read from the text; nothing was executed.

Is ARM and AArch64 Assembly safe to install?

Our automated static check of SKILL.md found no risky patterns, such as piping downloads into a shell, reading credential files or hidden Unicode. It is not a guarantee. Review the folder before installing.

What licence does ARM and AArch64 Assembly use?

ARM and AArch64 Assembly is published under the MIT licence (the repository's licence). It allows redistribution, so the full SKILL.md is shown on this page.

How many tokens does ARM and AArch64 Assembly use?

About 1.9k tokens (SKILL.md is roughly 7.6k characters). Agents keep only the skill's name and description in context until a task matches; then they load SKILL.md in full. Its references folder adds about 1.4k tokens, read only when the agent opens those files.

What are the alternatives to ARM and AArch64 Assembly?

Skills that share tags, products or a category with ARM and AArch64 Assembly: C64 Meatloaf Debug (idolpx/meatloaf, 128 stars), Embedded Stm32 (Mindrally/skills, 271 stars), Esp32 Firmware Engineer (alxv2016/folloup-sticky, 117 stars) and ExecuTorch Binary Size Reduction (pytorch/executorch, 5.1k stars). The comparison table on this page puts their stars, adoption, token cost, safety result and licence side by side.

Who maintains ARM and AArch64 Assembly?

mohitmishra786 (a GitHub user) maintains it in mohitmishra786/low-level-dev-skills, which has 252 GitHub stars. The repository holds 138 skills in this directory. The repository was last updated on June 27, 2026.

Source: mohitmishra786/low-level-dev-skills on GitHub. Facts on this page come from the repository at the commit we read; the author's words are quoted as theirs.