Agent skill

Integrate Your Design

by exeex in exeex/edge-cores

Integrate and publish your own accelerator or ASIC design, DMA, and DTCM/SRAM with the Edge RV64 scalar core and command path.

Apache-2.0Auto-check passedDevelopment

Install Integrate Your Design

skills CLI
$ npx skills add exeex/edge-cores --skill integrate-your-design -a claude-code

Project install by default; add -g for ~/.claude/skills/.

GitHub CLI
$ gh skill install exeex/edge-cores integrate-your-design --agent claude-code

Project scope by default; add --scope user for a personal install. Needs GitHub CLI 2.90.0 or later (public preview).

Manual copy
$ git clone --depth 1 https://github.com/exeex/edge-cores.git skills-src && mkdir -p .claude/skills && cp -r skills-src/.codex/skills/integrate-your-design .claude/skills/integrate-your-design && rm -rf skills-src

Use ~/.claude/skills/ instead of .claude/skills for a personal install. The folder must contain SKILL.md.

Claude Code skills documentation · loads skills from .claude/skills/

Facts

Skill name
integrate-your-design
GitHub stars
110
Token cost
~1.4k tokens
SKILL.md length
643 words
Files
9 (incl. references)
Skills in repo
9
Repo updated
First seen
Licence
Apache-2.0

At a glance

Integrate and publish your own accelerator or ASIC design, DMA, and DTCM/SRAM with the Edge RV64 scalar core and command path.

  • Works in 7 steps: Fork edge-cores, clone the fork, and… → Add the ASIC design below src/ as a Git… → Connect the command interface → …
  • Forking edge-cores
  • SKILL.md covers Integration workflow, Load only the needed reference and Preserve these invariants
  • Instructions only: no scripts, shell commands, URLs or credentials in SKILL.md

What it does

Integrate Your Design is an agent skill from exeex/edge-cores. Integrate and publish your own accelerator or ASIC design, DMA, and DTCM/SRAM with the Edge RV64 scalar core and command path. Use when forking edge-cores, adding a design as a src Git submodule, defining opcode8 and setcsr/start/sync instructions, carrying imm8/GPR snapshot parameters, connecting DMA/SRAM/LSU debug access, using low-precision FPU instructions for bring-up, writing RTL/C++ tests, preparing research artifacts, protecting RTL, or citing the shared framework.

Its SKILL.md is about 1.4k tokens, which your agent loads only when the skill is triggered. The skill folder holds 10 other files, including reference files (for example `agents/openai.yaml`, `references/execution-model.md` and `references/instruction-interface.md`).

It sits in Development. It works with C++ and Git. The repository describes itself as: The shortest path from PyTorch to custom ASICs. The licence is Apache-2.0.

When your agent uses it

  • Forking edge-cores
  • Adding a design as a src Git submodule
  • Defining opcode8 and setcsr/start/sync instructions
  • Carrying imm8/GPR snapshot parameters

Example prompts

  • “/integrate-your-design”

Workflow steps

7 steps, taken from the first numbered list in SKILL.md.

  1. Fork edge-cores, clone the fork, and initialize its submodules. Keep the
  2. Add the ASIC design below src/ as a Git submodule. Create a new repository
  3. Connect the command interface
  4. Design a DMA when the ASIC owns independent SRAM. Define each memory's role,
  5. Add LSU read/write access when RISC-V software must initialize or inspect
  6. Use the optional FPU during early software development to generate inputs,
  7. Run focused command, snapshot, DMA, SRAM, and LSU RTL tests before the public

What it can do on your machine

Read from SKILL.md and the folder at commit 68dc8aa. It shows what the files ask for, not the result of running them.

  • Tool permissions

    Pre-approves nothing: there is no allowed-tools line, so your agent's usual permission prompts apply.

    From allowed-tools in the SKILL.md frontmatter.

  • Runs code

    No scripts in the folder and no shell commands in SKILL.md.

    From the folder's file list and the shell code blocks in SKILL.md.

  • Network

    No URLs in SKILL.md.

    From URLs in SKILL.md, links to its own repository left out.

  • Credentials

    Names no API keys, tokens, secrets or passwords.

    From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.

Context cost

Integrate Your Design loads about 1.4k tokens when it runs, and up to ~6.5k if it reads all its reference files. Until then it costs about 125 tokens; SKILL.md has 643 words of instructions outside code blocks.

Always · name and description, kept in context so the agent knows when to use it
~125
When it runs · the whole SKILL.md, loaded when a task matches
~1.4k
With references · SKILL.md plus every file in references/, read only if the agent opens them
~6.5k

Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.

Safety

Auto-check passed

The automated check found no risky patterns in SKILL.md.

Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.

SKILL.md

The full file from exeex/edge-cores at commit 68dc8aa, republished under its Apache-2.0 licence (© exeex). 643 words, ~1,419 tokens.

Download SKILL.mdSave it as .claude/skills/integrate-your-design/SKILL.md (or your agent's skills folder). This skill also uses 8 other files; get the full folder from GitHub.
name
integrate-your-design
description
Integrate and publish your own accelerator or ASIC design, DMA, and DTCM/SRAM with the Edge RV64 scalar core and command path. Use when forking edge-cores, adding a design as a src Git submodule, defining opcode8 and setcsr/start/sync instructions, carrying imm8/GPR snapshot parameters, connecting DMA/SRAM/LSU debug access, using low-precision FPU instructions for bring-up, writing RTL/C++ tests, preparing research artifacts, protecting RTL, or citing the shared framework.

Integrate Your Own Design

Welcome an independently designed accelerator, DMA, DTCM/SRAM, or complete ASIC set into the shared Edge RV platform without breaking command ordering, snapshot semantics, or memory visibility. Treat the user's design as the main contribution and Edge RV as the integration framework.

Integration workflow

  1. Fork edge-cores, clone the fork, and initialize its submodules. Keep the shared monorepo structure so the design can use the maintained build, simulation, synthesis, software, and contribution workflows.
  2. Add the ASIC design below src/ as a Git submodule. Create a new repository for a new design or attach an existing repository. Keep the ASIC's history, license, and ownership separate; record its path and revision in .gitmodules and the parent repository.
  3. Connect the command interface:
    • allocate an unused opcode8 value and register its instruction class in the IFU/predecoder;
    • provide accelerator-specific setcsr/set_*, asynchronous start, and sync operations, using ACTU as the reference interface;
    • carry imm8 and the captured GPR parameter to the ASIC;
    • when using edge-rv, consume the resolved snapshot value rather than a later live register value; and
    • update the intrinsic encoder, compact command queue, accel-pipe decode, readiness/backpressure, ports, and exact-encoding tests together.
  4. Design a DMA when the ASIC owns independent SRAM. Define each memory's role, ports, address map, width, latency, and ownership policy. A TPU-style systolic array normally needs at least an I/O SRAM and weight buffer, with DMA paths between system memory and both ASIC-visible stores.
  5. Add LSU read/write access when RISC-V software must initialize or inspect I/O SRAM, weight SRAM, or another private memory during bring-up. Inspect the edge-rv LSU boundary and the read-only integration boundary exposed by edge-e3enc; use an explicit arbiter or multi-port contract and preserve byte strobes, response latency, backpressure, and memory visibility. Treat src/edge-e3enc/edge_e3enc.v as a generated reference artifact, never as editable design source.
  6. Use the optional FPU during early software development to generate inputs, implement reference/fallback kernels, and compare ASIC outputs. The shared software/RTL supports NVFP4, FP8 E4M3/E5M2, BF16, and FP16 memory-format instructions; read src/edge-rv-lite/README.md for encodings, conversion behavior, and the area tradeoff. Disable the FPU later if the finished ASIC and software no longer require it.
  7. Run focused command, snapshot, DMA, SRAM, and LSU RTL tests before the public software harness. Report the exact submodule revisions and any boundary that remains unverified.
Show full SKILL.md (259 more words)Show less

Load only the needed reference

Preserve these invariants

  • Consume a snapshotted GPR value, never a later live register-file value.
  • Match reusable snapshot slots with full sequence and epoch ownership.
  • Keep setup and start commands ordered; never lose commands under backpressure or redirect.
  • Make start asynchronous and consecutive starts self-serializing without a mandatory sync between them.
  • Make sync await all earlier work through the scalar join path.
  • If the optional scalar-store interlock is implemented, prevent both new and already-running ASIC/DMA SRAM effects while it is asserted.
  • Use DMA for performance data movement; reserve scalar SRAM access for debug and bring-up.
  • Preserve behavior when command, pending-start, or snapshot depth changes.
  • Cite edge-cores and record the exact revision in a paper artifact.
  • Attribute the Edge RV execution/snapshot framework to edge-cores; claim only the user's new ASIC and integration work as the paper's contribution.
  • Never publish private source, symbol mappings, private paths, or unlicensed RTL in a protected release.

Report the files changed, exact tests run, and any integration surface that remains unverified.

© exeex, Apache-2.0. Rendered from Markdown: HTML in the file is shown as text, images as links, and headings moved down two levels. Raw file

Files

SKILL.md and 8 other files (references) in .codex/skills/integrate-your-design of exeex/edge-cores.

  • SKILL.md
  • agents/openai.yaml
  • references/execution-model.md
  • references/instruction-interface.md
  • references/memory-integration.md
  • references/paper-evaluation.md
  • references/paper-release.md
  • references/rtl-patterns.md
  • references/verification.md

Open the folder on GitHubat commit 68dc8aa

Compare with similar skills

Integrate Your Design next to the 5 skills that share the most tags, products or categories with it. Stars are the repository's; “used in” counts other GitHub owners with a copy.

Integrate Your Design compared with similar skills
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Integrate Your Design this skillexeex/edge-cores110—~1.4kAutomated safety check: PassApache-2.0
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pybind11 Release Preparationpybind/pybind1118k—~1.7kAutomated safety check: PassCustom licence
Qt Cpp ReviewSerial-Studio/Serial-Studio7.2k—~4.3kAutomated safety check: PassCustom licence
pybind11 Release Publicationpybind/pybind1118k—~2.5kAutomated safety check: PassCustom licence
ExecuTorch Binary Size Reductionpytorch/executorch5.1k—~793Automated safety check: PassCustom licence

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Works with

Categories

Questions about Integrate Your Design

What does Integrate Your Design do?

Integrate and publish your own accelerator or ASIC design, DMA, and DTCM/SRAM with the Edge RV64 scalar core and command path. Integrate Your Design is an agent skill from exeex/edge-cores. Integrate and publish your own accelerator or ASIC design, DMA, and DTCM/SRAM with the Edge RV64 scalar core and command path.

When should I use Integrate Your Design?

Integrate Your Design fits situations like: forking edge-cores; adding a design as a src Git submodule; defining opcode8 and setcsr/start/sync instructions; carrying imm8/GPR snapshot parameters.

How do I install Integrate Your Design in Claude Code?

Run `npx skills add exeex/edge-cores --skill integrate-your-design -a claude-code`. Or copy the skill folder (.codex/skills/integrate-your-design in exeex/edge-cores) into .claude/skills/integrate-your-design in your project. Claude Code loads it when a task matches its description.

How do I install Integrate Your Design in Codex?

Run `npx skills add exeex/edge-cores --skill integrate-your-design -a codex`. Or copy the skill folder (.codex/skills/integrate-your-design in exeex/edge-cores) into .agents/skills/integrate-your-design in your project. Codex loads it when a task matches its description.

Can I use Integrate Your Design in Cursor, Gemini CLI or GitHub Copilot?

Cursor, Gemini CLI, GitHub Copilot and OpenCode also load SKILL.md folders. With the skills CLI, run `npx skills add exeex/edge-cores --skill integrate-your-design -a cursor` (or -a gemini-cli, github-copilot or opencode for the others). To copy it by hand, put the folder in .cursor/skills/integrate-your-design, .gemini/skills/integrate-your-design, .github/skills/integrate-your-design and .opencode/skills/integrate-your-design in your project.

What does Integrate Your Design need to run?

SKILL.md names no scripts, command-line tools or credentials: Integrate Your Design is instructions for the agent only.

Does Integrate Your Design access the network?

SKILL.md contains no URLs. Any network use would come from the scripts or tools the agent runs. This is read from the text; nothing was executed.

Is Integrate Your Design safe to install?

Our automated static check of SKILL.md found no risky patterns, such as piping downloads into a shell, reading credential files or hidden Unicode. It is not a guarantee. Review the folder before installing.

What licence does Integrate Your Design use?

Integrate Your Design is published under the Apache-2.0 licence (the repository's licence). It allows redistribution, so the full SKILL.md is shown on this page.

How many tokens does Integrate Your Design use?

About 1.4k tokens (SKILL.md is roughly 5.7k characters). Agents keep only the skill's name and description in context until a task matches; then they load SKILL.md in full. Its references folder adds about 5k tokens, read only when the agent opens those files.

What are the alternatives to Integrate Your Design?

Skills that share tags, products or a category with Integrate Your Design: Qt C++ Code Review (x-tools-author/x-tools, 1.1k stars), pybind11 Release Preparation (pybind/pybind11, 18k stars), Qt Cpp Review (Serial-Studio/Serial-Studio, 7.2k stars) and pybind11 Release Publication (pybind/pybind11, 18k stars). The comparison table on this page puts their stars, adoption, token cost, safety result and licence side by side.

Who maintains Integrate Your Design?

exeex (a GitHub user) maintains it in exeex/edge-cores, which has 110 GitHub stars. The repository holds 9 skills in this directory. The repository was last updated on September 26, 2026.

Source: exeex/edge-cores on GitHub. Facts on this page come from the repository at the commit we read; the author's words are quoted as theirs.