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Official agent skill

Extract Xpu Kernel Asm

by intel in intel/torch-xpu-ops

Extract Intel GPU ISA (assembly) from any XPU kernel. An agent skill from intel/torch-xpu-ops.

OfficialApache-2.0Auto-check passedAI & LLM Engineering

Install Extract Xpu Kernel Asm

skills CLI
$ npx skills add intel/torch-xpu-ops --skill extract-xpu-kernel-asm -a claude-code

Project install by default; add -g for ~/.claude/skills/.

GitHub CLI
$ gh skill install intel/torch-xpu-ops extract-xpu-kernel-asm --agent claude-code

Project scope by default; add --scope user for a personal install. Needs GitHub CLI 2.90.0 or later (public preview).

Manual copy
$ git clone --depth 1 https://github.com/intel/torch-xpu-ops.git skills-src && mkdir -p .claude/skills && cp -r skills-src/.claude/skills/extract-xpu-kernel-asm .claude/skills/extract-xpu-kernel-asm && rm -rf skills-src

Use ~/.claude/skills/ instead of .claude/skills for a personal install. The folder must contain SKILL.md.

Claude Code skills documentation · loads skills from .claude/skills/

Facts

Skill name
extract-xpu-kernel-asm
GitHub stars
115
Token cost
~2.9k tokens
SKILL.md length
717 words
Files
1
Skills in repo
29
Repo updated
First seen
Licence
Apache-2.0

At a glance

Extract Intel GPU ISA (assembly) from any XPU kernel. An agent skill from intel/torch-xpu-ops.

  • Works in 5 steps: Locate tools → Pin the actually-launched kernel → Classify scenario → …
  • Asked to extract ASM
  • SKILL.md covers Compilation Stack, When to use, When NOT to use and Steps, plus 1 more section
  • Instructions only: no scripts, shell commands, URLs or credentials in SKILL.md

What it does

Extract Xpu Kernel Asm is an agent skill from intel/torch-xpu-ops, published by the product's own GitHub organization. Extract Intel GPU ISA (assembly) from any XPU kernel. Classifies the codegen path (SYCL AOT, SYCL JIT, Triton, or oneDNN ngen) and delegates to the matching extraction skill. Use when asked to extract ASM, disassemble XPU kernels, get GPU ISA for an aten op, dump shader for PyTorch XPU, or disassemble a standalone DPC++/Triton binary.

Its SKILL.md is about 2.9k tokens, which your agent loads only when the skill is triggered. It is a single SKILL.md file with no bundled scripts.

It sits in AI & LLM Engineering, covering Project scaffolding and Deep learning. It works with C++ and PyTorch. The licence is Apache-2.0.

When your agent uses it

  • Asked to extract ASM
  • Disassemble XPU kernels
  • Get GPU ISA for an aten op
  • Dump shader for PyTorch XPU

Example prompts

  • “/extract-xpu-kernel-asm”

Requirements

  • Python 3

Workflow steps

5 steps, taken from the step headings in SKILL.md.

  1. Locate tools
  2. Pin the actually-launched kernel
  3. Classify scenario
  4. Dispatch to atomic skill
  5. Emit normalized outputs

What it can do on your machine

Read from SKILL.md and the folder at commit a033aa5. It shows what the files ask for, not the result of running them.

  • Tool permissions

    Pre-approves nothing: there is no allowed-tools line, so your agent's usual permission prompts apply.

    From allowed-tools in the SKILL.md frontmatter.

  • Runs code

    No scripts in the folder and no shell commands in SKILL.md (its code samples are bash, python and cpp).

    From the folder's file list and the shell code blocks in SKILL.md.

  • Network

    No URLs in SKILL.md.

    From URLs in SKILL.md, links to its own repository left out.

  • Credentials

    Names no API keys, tokens, secrets or passwords.

    From names ending in _API_KEY, _TOKEN, _SECRET, _KEY or _PASSWORD in SKILL.md.

Context cost

Extract Xpu Kernel Asm loads about 2.9k tokens when it runs. Until then it costs about 90 tokens; SKILL.md has 717 words of instructions outside code blocks.

Always · name and description, kept in context so the agent knows when to use it
~90
When it runs · the whole SKILL.md, loaded when a task matches
~2.9k

Estimates: characters ÷ 4, the usual rule of thumb; real counts depend on the model's tokenizer. Scripts and assets cost tokens only if the agent reads them.

Safety

Auto-check passed

The automated check found no risky patterns in SKILL.md.

Automated static check — not a guarantee. Review scripts before installing. It scans the text of SKILL.md for risky patterns (piping downloads into a shell, reading credential files, hidden Unicode, destructive commands); files beside SKILL.md are not scanned.

SKILL.md

The full file from intel/torch-xpu-ops at commit a033aa5, republished under its Apache-2.0 licence (© intel). 717 words, ~2,947 tokens.

Download SKILL.mdSave it as .claude/skills/extract-xpu-kernel-asm/SKILL.md (or your agent's skills folder).
name
extract-xpu-kernel-asm
description
Extract Intel GPU ISA (assembly) from any XPU kernel. Classifies the codegen path (SYCL AOT, SYCL JIT, Triton, or oneDNN ngen) and delegates to the matching extraction skill. Use when asked to extract ASM, disassemble XPU kernels, get GPU ISA for an aten op, dump shader for PyTorch XPU, or disassemble a standalone DPC++/Triton binary.

Extract XPU Kernel ASM (Dispatcher)

Classify which codegen path produced the kernel and delegate to the matching atomic skill to extract its Intel GPU ISA.

Compilation Stack

All XPU kernel compilation ultimately produces the same thing: GPU ISA bytes. The skills are separated not by compilation logic (which is largely identical), but by where the zebin lives:

┌─────────────────────────────────────────────────────────────────┐
│              Shared Compilation Stack                            │
│  SYCL/C++ → LLVM IR → SPIR-V → IGC → zebin (GPU ISA)          │
│                                                                 │
│  • -g / -gline-tables-only acts at frontend (SYCL → LLVM IR)   │
│  • Debug info flows: !dbg → OpLine → DebugLoc → .debug_line    │
│  • JIT vs AOT: same IR pipeline, different WHEN it runs         │
└─────────────────────────────────────────────────────────────────┘

┌───────────────┬──────────────────────────────────────────────────┐
│ Scenario      │ Where is the zebin? How to get it?               │
├───────────────┼──────────────────────────────────────────────────┤
│ sycl-aot      │ Embedded in host binary at build time            │
│               │ → DumpZEBin=1 NEOReadDebugKeys=1 → ocloc disasm  │
├───────────────┼──────────────────────────────────────────────────┤
│ sycl-jit      │ Generated at first launch, only in memory        │
│               │ → IGC_ShaderDumpEnable=1 → dump dir → .asm/.elf  │
├───────────────┼──────────────────────────────────────────────────┤
│ triton        │ Triton compiler → SPIR-V → IGC JIT at launch     │
│               │ → IGC_ShaderDumpEnable=1 (same as sycl-jit)      │
├───────────────┼──────────────────────────────────────────────────┤
│ onednn (ngen) │ BYPASSES the entire SPIR-V/IGC stack             │
│               │ Own JIT: ngen → raw ISA bytes (not zebin ELF)    │
│               │ → ONEDNN_JIT_DUMP=1 → IGA ctypes disassembly    │
└───────────────┴──────────────────────────────────────────────────┘

Key implications for downstream:

  • sycl-aot, sycl-jit, triton all produce zebin ELF → same ocloc disasm / readelf / .debug_line workflow applies.
  • onednn produces raw ISA bytes (no ELF wrapper, no .debug_line) → requires IGA ctypes, pattern-recognition only for source mapping.

When to use

  • You have a hot kernel (from profiler / unitrace) and need its ISA.
  • Entry points: PyTorch op, standalone @triton.jit, standalone DPC++.
  • Hardware: Intel XPU (PVC / BMG-G31 / DG2 / LNL / ARL / MTL / PTL).

When NOT to use

  • You only want wall-clock timing — use the profiler directly.
  • You only want Triton IR (not ISA) — read ~/.triton/cache/.

Steps

Step 0: Locate tools

Key tools are NOT always on PATH. Probe before proceeding:

bash
# Detect oneAPI root: check env vars first, then common install locations
ONEAPI=${ONEAPI_ROOT:-${CMPLR_ROOT:+${CMPLR_ROOT%/*}}}
if [ -z "$ONEAPI" ]; then
  for d in /opt/intel/oneapi ~/intel/oneapi /usr/local/oneapi; do
    [ -d "$d" ] && ONEAPI="$d" && break
  done
fi

# ocloc (for disassembling zebin ELFs)
command -v ocloc >/dev/null || echo "ocloc not found; source oneapi-vars.sh"

# libiga64.so (for oneDNN ngen disassembly only)
IGA_LIB=$(test -n "$ONEAPI" && find "$ONEAPI" -name 'libiga64.so' 2>/dev/null | head -1)
Step 1: Pin the actually-launched kernel

Identify which kernel was executed on the GPU. The kernel name determines which sub-skill to dispatch to (oneDNN vs Triton vs SYCL).

Preferred: unitrace (covers ALL code paths including native-handle):

bash
unitrace -d <repro_cmd>

Parse the == L0 Backend == table — each data row has the kernel name as the first double-quoted field. Skip rows starting with ze* (those are API calls, not GPU kernels). Extract and deduplicate kernel names.

Probe unitrace location in order: $UNITRACE env var → command -v unitrace → $UNITRACE_HOME/unitrace → <pti-gpu-build>/tools/unitrace/build/unitrace.

Fallback: SYCL_UR_TRACE (zero-dep, but has a blind spot):

bash
SYCL_UR_TRACE=-1 <repro_cmd> 2>&1 | grep -oP 'pKernelName = 0x[0-9a-f]+ \(\K[^)]+'

WARNING: SYCL_UR_TRACE is BLIND to kernels created via urKernelCreateWithNativeHandle (oneDNN ngen, SYCL-TLA, Triton-xpu ≥ 3.7.0). If the list is empty but the workload clearly ran GPU kernels, you MUST install unitrace before proceeding. Do NOT extract ASM blindly.

Step 2: Classify scenario
SignalScenario
Kernel = gemm_kernel / gen_conv_kernel / routed via mkldnn::*onednn
Kernel = triton_* or standalone @triton.jittriton
Kernel = _ZTS… AND AOT path active for current devicesycl-aot
Kernel = _ZTS… AND JIT path active (no AOT or target mismatch)sycl-jit

For _ZTS… kernels, determine AOT vs JIT:

A binary may contain __CLANG_OFFLOAD_BUNDLE but its AOT targets may not cover the current device (e.g. built for PVC, running on BMG → runtime falls back to JIT via SPIR-V). Test which path is actually active:

Method A (preferred): unitrace Kernel Properties

If unitrace was already used in Step 1, check the Compiled column:

  • AOT → scenario = sycl-aot
  • JIT → scenario = sycl-jit

Method B: IGC dump probe

IGC is only invoked at runtime for JIT compilation. If IGC dump files appear, the kernel was JIT-compiled:

bash
# Quick test: if IGC produces dump files, JIT path is active
rm -rf /tmp/igc_probe && mkdir -p /tmp/igc_probe
IGC_ShaderDumpEnable=1 IGC_ShaderDumpPidDisable=1 IGC_DumpToCustomDir=/tmp/igc_probe <repro_cmd> 2>/dev/null
if ls /tmp/igc_probe/*.asm 2>/dev/null | grep -q .; then
  SCENARIO=sycl-jit
else
  SCENARIO=sycl-aot
fi
rm -rf /tmp/igc_probe

NOTE: Do NOT use DumpZEBin=1 for classification — it produces .elf files for both AOT and JIT scenarios (the runtime always has a zebin to submit, regardless of how it was produced).

If ambiguous → ask the user.

Show full SKILL.md (260 more words)Show less
Step 3: Dispatch to atomic skill
onednn   → extract-asm-onednn
triton   → extract-asm-triton
sycl-aot → extract-asm-syclkernel-aot
sycl-jit → extract-asm-syclkernel-jit
Step 4: Emit normalized outputs

All fields REQUIRED:

FieldDescription
input-kernelUser's kernel identifier (echoed verbatim)
scenarioonednn / triton / sycl-aot / sycl-jit
asm-dirAbsolute path to output directory
asm-fileAbsolute path to the chosen .asm file
kernel-nameKernel name as it appears in asm-file
launch-evidence≥3 sentences explaining WHY this is the correct kernel

Examples

Each example shows the dispatcher's classification — how to identify the scenario and what output to expect. The detailed extraction steps are in the respective sub-skill; these examples only demonstrate the classification signal and final result.

Example 1 — oneDNN ngen: BF16 GEMM via aten::matmul

Repro:

python
import torch
a = torch.randn(4096, 4096, dtype=torch.bfloat16, device='xpu')
b = torch.randn(4096, 4096, dtype=torch.bfloat16, device='xpu')
c = a @ b; torch.xpu.synchronize()

Classification signal: unitrace shows gemm_kernel → scenario = onednn → delegate to extract-asm-onednn.

Expected result:

scenario:    onednn
asm-file:    <workdir>/gemm.asm
kernel-name: gemm_kernel
validation:  grep -c dpas gemm.asm → non-zero (GEMM uses dpas instructions)
Example 2 — Triton: torch.compile(softmax)

Repro:

python
import torch
@torch.compile
def fn(x): return torch.softmax(x, dim=-1)
x = torch.randn(1024, 1024, device='xpu')
fn(x); torch.xpu.synchronize()

Classification signal: TORCH_LOGS=output_code shows a triton_per_fused_*softmax* kernel name → scenario = triton → delegate to extract-asm-triton.

Expected result:

scenario:    triton
asm-file:    <igc_dump>/OCL_asm*_simd*_entry_*.asm
kernel-name: triton_per_fused_*softmax* (exact name varies by PyTorch version)
validation:  grep 'libdevice.exp' <asm-file> confirms softmax exp computation
Example 3 — SYCL AOT: standalone DPC++ binary

Repro:

cpp
// vec_add.cpp
#include <sycl/sycl.hpp>
class VecAddKernel;
int main() {
    sycl::queue q;
    constexpr int N = 1 << 24;
    float *a = sycl::malloc_device<float>(N, q);
    float *c = sycl::malloc_device<float>(N, q);
    q.parallel_for<VecAddKernel>(N, [=](int i) { c[i] = a[i] + 1.0f; }).wait();
    sycl::free(a, q); sycl::free(c, q);
}
bash
icpx -fsycl -O2 -fsycl-targets=spir64_gen -Xs "-device <dev>" vec_add.cpp -o vec_add

Classification signal: unitrace shows VecAddKernel with Compiled = AOT → scenario = sycl-aot → delegate to extract-asm-syclkernel-aot.

Expected result:

scenario:    sycl-aot
asm-file:    <workdir>/<name>_dump/.text._ZTS12VecAddKernel.asm
kernel-name: _ZTS12VecAddKernel
validation:  c++filt _ZTS12VecAddKernel → VecAddKernel
Example 4 — SYCL AOT: libtorch_xpu.so

Repro:

python
import torch
x = torch.randn(1024, dtype=torch.float, device='xpu')
y = x + 1.0; torch.xpu.synchronize()

Classification signal: unitrace shows the kernel with Compiled = AOT → scenario = sycl-aot → delegate to extract-asm-syclkernel-aot.

Expected result:

scenario:    sycl-aot
asm-file:    <workdir>/<name>_dump/.text._ZTSN2at6native3xpu...E.asm
kernel-name: matches the demangled kernel from c++filt
Example 5 — SYCL JIT: standalone DPC++ without AOT target

Repro:

cpp
// shift_reduce.cpp
#include <sycl/sycl.hpp>
class ShiftReduceKernel;
int main() {
    sycl::queue q;
    auto *buf = sycl::malloc_device<int>(1024, q);
    q.parallel_for<ShiftReduceKernel>(
        sycl::nd_range<1>(1024, 32), [=](sycl::nd_item<1> it) {
        int val = buf[it.get_global_id(0)];
        val += sycl::shift_group_left(it.get_sub_group(), val, 1);
        buf[it.get_global_id(0)] = val;
    }).wait();
    sycl::free(buf, q);
}
bash
icpx -fsycl -O2 -g -fsycl-targets=spir64 shift_reduce.cpp -o shift_reduce

Classification signal: unitrace shows ShiftReduceKernel with Compiled = JIT → scenario = sycl-jit → delegate to extract-asm-syclkernel-jit.

Alternatively: IGC_ShaderDumpEnable=1 ./shift_reduce produces .asm files in the IGC dump directory (confirming IGC was invoked at runtime = JIT).

Expected result:

scenario:    sycl-jit
asm-file:    <igc_dump>/OCL_asm*_simd*_entry_*.asm
kernel-name: _ZTS17ShiftReduceKernel
validation:  compiled with -g → grep '// Line' shows source annotations
Example 6 — SYCL JIT fallback: AOT mismatch

Repro:

cpp
// vec_add.cpp (same as Example 3)
bash
# Compile AOT for PVC, but run on BMG → runtime falls back to JIT via SPIR-V
icpx -fsycl -O2 -g -fsycl-targets=spir64_gen -Xs "-device pvc" vec_add.cpp -o vec_add_pvc

Classification signal: unitrace may crash on cross-device AOT binaries. Use IGC probe instead: IGC_ShaderDumpEnable=1 ./vec_add_pvc produces .asm files → IGC was called at runtime → JIT fallback confirmed.

Expected result:

scenario:    sycl-jit
asm-file:    <igc_dump>/OCL_asm*_simd*_entry_*.asm
kernel-name: _ZTSN4sycl3_V16detail19__pf_kernel_wrapperI12VecAddKernelEE
validation:  compiled with -g → grep '// Line' shows source annotations
             .platform shows XE2 (BMG), not PVC

© intel, Apache-2.0. Rendered from Markdown: HTML in the file is shown as text, images as links, and headings moved down two levels. Raw file

Files

Just SKILL.md in .claude/skills/extract-xpu-kernel-asm of intel/torch-xpu-ops.

Open the folder on GitHubat commit a033aa5

Compare with similar skills

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Works with

Categories

Questions about Extract Xpu Kernel Asm

What does Extract Xpu Kernel Asm do?

Extract Intel GPU ISA (assembly) from any XPU kernel. An agent skill from intel/torch-xpu-ops. Extract Xpu Kernel Asm is an agent skill from intel/torch-xpu-ops, published by the product's own GitHub organization. Extract Intel GPU ISA (assembly) from any XPU kernel.

When should I use Extract Xpu Kernel Asm?

Extract Xpu Kernel Asm fits situations like: asked to extract ASM; disassemble XPU kernels; get GPU ISA for an aten op; dump shader for PyTorch XPU.

How do I install Extract Xpu Kernel Asm in Claude Code?

Run `npx skills add intel/torch-xpu-ops --skill extract-xpu-kernel-asm -a claude-code`. Or copy the skill folder (.claude/skills/extract-xpu-kernel-asm in intel/torch-xpu-ops) into .claude/skills/extract-xpu-kernel-asm in your project. Claude Code loads it when a task matches its description.

How do I install Extract Xpu Kernel Asm in Codex?

Run `npx skills add intel/torch-xpu-ops --skill extract-xpu-kernel-asm -a codex`. Or copy the skill folder (.claude/skills/extract-xpu-kernel-asm in intel/torch-xpu-ops) into .agents/skills/extract-xpu-kernel-asm in your project. Codex loads it when a task matches its description.

Can I use Extract Xpu Kernel Asm in Cursor, Gemini CLI or GitHub Copilot?

Cursor, Gemini CLI, GitHub Copilot and OpenCode also load SKILL.md folders. With the skills CLI, run `npx skills add intel/torch-xpu-ops --skill extract-xpu-kernel-asm -a cursor` (or -a gemini-cli, github-copilot or opencode for the others). To copy it by hand, put the folder in .cursor/skills/extract-xpu-kernel-asm, .gemini/skills/extract-xpu-kernel-asm, .github/skills/extract-xpu-kernel-asm and .opencode/skills/extract-xpu-kernel-asm in your project.

What does Extract Xpu Kernel Asm need to run?

SKILL.md names no scripts, command-line tools or credentials: Extract Xpu Kernel Asm is instructions for the agent only. Our summary lists: Python 3.

Does Extract Xpu Kernel Asm access the network?

SKILL.md contains no URLs. Any network use would come from the scripts or tools the agent runs. This is read from the text; nothing was executed.

Is Extract Xpu Kernel Asm safe to install?

Our automated static check of SKILL.md found no risky patterns, such as piping downloads into a shell, reading credential files or hidden Unicode. It is not a guarantee. Review the folder before installing.

What licence does Extract Xpu Kernel Asm use?

Extract Xpu Kernel Asm is published under the Apache-2.0 licence (the repository's licence). It allows redistribution, so the full SKILL.md is shown on this page.

How many tokens does Extract Xpu Kernel Asm use?

About 2.9k tokens (SKILL.md is roughly 12k characters). Agents keep only the skill's name and description in context until a task matches; then they load SKILL.md in full.

What are the alternatives to Extract Xpu Kernel Asm?

Skills that share tags, products or a category with Extract Xpu Kernel Asm: Matlab Deploy AI Model (matlab/matlab-agentic-toolkit, 1.1k stars), Ako4all (TongmingLAIC/AKO4ALL, 369 stars), Paddle Op Dev (PaddlePaddle/Paddle, 24k stars) and Embedded AI Deployment (matlab/agent-skills-playground, 181 stars). The comparison table on this page puts their stars, adoption, token cost, safety result and licence side by side.

Who maintains Extract Xpu Kernel Asm?

intel (a GitHub organization, an official publisher) maintains it in intel/torch-xpu-ops, which has 115 GitHub stars. The repository holds 29 skills in this directory. The repository was last updated on October 8, 2026.

Source: intel/torch-xpu-ops on GitHub. Facts on this page come from the repository at the commit we read; the author's words are quoted as theirs.